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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:015328/0116   Pages: 16
Recorded: 05/21/2004
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 55
1
Patent #:
5011791
Issue Dt:
04/30/1991
Application #:
07305575
Filing Dt:
02/03/1989
Title:
FUSIBLE LINK WITH BUILT-IN REDUNDANCY
2
Patent #:
5028559
Issue Dt:
07/02/1991
Application #:
07327632
Filing Dt:
03/23/1989
Title:
FABRICATION OF DEVICES HAVING LATERALLY ISOLATED SEMICONDUCTOR REGIONS
3
Patent #:
5004703
Issue Dt:
04/02/1991
Application #:
07382947
Filing Dt:
07/21/1989
Title:
MULTIPLE TRENCH SEMICONDUCTOR STRUCTURE METHOD
4
Patent #:
4994406
Issue Dt:
02/19/1991
Application #:
07431420
Filing Dt:
11/03/1989
Title:
METHOD OF FABRICATING SEMICONDUCTOR DEVICES HAVING DEEP AND SHALLOW INSOLATION STRUCTURES
5
Patent #:
5108946
Issue Dt:
04/28/1992
Application #:
07559460
Filing Dt:
07/27/1990
Title:
METHOD OF FORMING PLANAR ISOLATION REGIONS
6
Patent #:
5026665
Issue Dt:
06/25/1991
Application #:
07632564
Filing Dt:
12/24/1990
Title:
SEMICONDUCTOR DEVICE ELECTRODE METHOD
7
Patent #:
5397912
Issue Dt:
03/14/1995
Application #:
07801282
Filing Dt:
12/02/1991
Title:
LATERAL BIPOLAR TRANSISTOR
8
Patent #:
5418410
Issue Dt:
05/23/1995
Application #:
08067449
Filing Dt:
05/25/1993
Title:
LEADING EDGE BLANKING CIRCUIT
9
Patent #:
5486481
Issue Dt:
01/23/1996
Application #:
08342476
Filing Dt:
11/21/1994
Title:
METHOD FOR FORMING A LATERAL BIPOLAR TRANSISTOR
10
Patent #:
5512785
Issue Dt:
04/30/1996
Application #:
08347522
Filing Dt:
11/30/1994
Title:
SEMICONDUCTOR DEVICE HAVING AN EMITTER TERMINAL SEPARATED FROM A BASE TERMINAL BY A COMPOSITE NITRIDE/OXIDE LAYER
11
Patent #:
6796501
Issue Dt:
09/28/2004
Application #:
09845114
Filing Dt:
04/30/2001
Publication #:
US20020158126
Pub Dt:
10/31/2002
Title:
SMART CARD READER CIRCUIT AND METHOD OF MONITORING
12
Patent #:
6677672
Issue Dt:
01/13/2004
Application #:
10133527
Filing Dt:
04/26/2002
Publication #:
US20030209804
Pub Dt:
11/13/2003
Title:
STRUCTURE AND METHOD OF FORMING A MULTIPLE LEADFRAME SEMICONDUCTOR DEVICE
13
Patent #:
6759891
Issue Dt:
07/06/2004
Application #:
10133761
Filing Dt:
04/29/2002
Publication #:
US20030201816
Pub Dt:
10/30/2003
Title:
THERMAL SHUTDOWN CIRCUIT WITH HYSTERESIS AND METHOD OF USING
14
Patent #:
6744313
Issue Dt:
06/01/2004
Application #:
10138973
Filing Dt:
05/02/2002
Publication #:
US20030206057
Pub Dt:
11/06/2003
Title:
POWER AMPLIFIER DRIVER AND METHOD OF USING
15
Patent #:
6664773
Issue Dt:
12/16/2003
Application #:
10153986
Filing Dt:
05/23/2002
Publication #:
US20030218454
Pub Dt:
11/27/2003
Title:
VOLTAGE MODE VOLTAGE REGULATOR WITH CURRENT MODE START-UP
16
Patent #:
6791390
Issue Dt:
09/14/2004
Application #:
10156285
Filing Dt:
05/28/2002
Publication #:
US20030224624
Pub Dt:
12/04/2003
Title:
METHOD OF FORMING A VOLTAGE REGULATOR SEMICONDUCTOR DEVICE HAVING FEEDBACK AND STRUCTURE THEREFOR
17
Patent #:
6953980
Issue Dt:
10/11/2005
Application #:
10166288
Filing Dt:
06/11/2002
Publication #:
US20030228848
Pub Dt:
12/11/2003
Title:
SEMICONDUCTOR FILTER CIRCUIT AND METHOD
18
Patent #:
6747341
Issue Dt:
06/08/2004
Application #:
10183287
Filing Dt:
06/27/2002
Publication #:
US20040000702
Pub Dt:
01/01/2004
Title:
INTEGRATED CIRCUIT AND LAMINATED LEADFRAME PACKAGE
19
Patent #:
6852634
Issue Dt:
02/08/2005
Application #:
10184187
Filing Dt:
06/27/2002
Publication #:
US20040002222
Pub Dt:
01/01/2004
Title:
LOW COST METHOD OF PROVIDING A SEMICONDUCTOR DEVICE HAVING A HIGH CHANNEL DENSITY
20
Patent #:
6674305
Issue Dt:
01/06/2004
Application #:
10189748
Filing Dt:
07/08/2002
Publication #:
US20040004497
Pub Dt:
01/08/2004
Title:
METHOD OF FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR
21
Patent #:
6713317
Issue Dt:
03/30/2004
Application #:
10215279
Filing Dt:
08/12/2002
Publication #:
US20040029312
Pub Dt:
02/12/2004
Title:
INTEGRATED CIRCUIT AND LAMINATED LEADFRAME PACKAGE
22
Patent #:
6876249
Issue Dt:
04/05/2005
Application #:
10217497
Filing Dt:
08/13/2002
Publication #:
US20040032293
Pub Dt:
02/19/2004
Title:
CIRCUIT AND METHOD FOR A PROGRAMMABLE REFERENCE VOLTAGE
23
Patent #:
6747477
Issue Dt:
06/08/2004
Application #:
10217661
Filing Dt:
08/13/2002
Publication #:
US20040032281
Pub Dt:
02/19/2004
Title:
PROGRAMMABLE DATA DEVICE AND METHOD THEREFOR
24
Patent #:
6803317
Issue Dt:
10/12/2004
Application #:
10219167
Filing Dt:
08/16/2002
Publication #:
US20040033694
Pub Dt:
02/19/2004
Title:
METHOD OF MAKING A VERTICAL GATE SEMICONDUCTOR DEVICE
25
Patent #:
7045845
Issue Dt:
05/16/2006
Application #:
10219190
Filing Dt:
08/16/2002
Publication #:
US20040031981
Pub Dt:
02/19/2004
Title:
SELF-ALIGNED VERTICAL GATE SEMICONDUCTOR DEVICE
26
Patent #:
6809559
Issue Dt:
10/26/2004
Application #:
10228374
Filing Dt:
08/27/2002
Publication #:
US20040041151
Pub Dt:
03/04/2004
Title:
METHOD OF FORMING A POWER DEVICE AND STRUCTURE THEREFOR
27
Patent #:
6787392
Issue Dt:
09/07/2004
Application #:
10237123
Filing Dt:
09/09/2002
Publication #:
US20040048413
Pub Dt:
03/11/2004
Title:
STRUCTURE AND METHOD OF DIRECT CHIP ATTACH
28
Patent #:
6768186
Issue Dt:
07/27/2004
Application #:
10270401
Filing Dt:
10/15/2002
Publication #:
US20040070062
Pub Dt:
04/15/2004
Title:
SEMICONDUCTOR DEVICE AND LAMINATED LEADFRAME PACKAGE
29
Patent #:
6717473
Issue Dt:
04/06/2004
Application #:
10270413
Filing Dt:
10/15/2002
Publication #:
US20040070456
Pub Dt:
04/15/2004
Title:
METHOD OF FORMING AN AUDIO AMPLIFIER VOLTAGE REFERENCE AND STRUCTURE THEREFOR
30
Patent #:
6753228
Issue Dt:
06/22/2004
Application #:
10270419
Filing Dt:
10/15/2002
Publication #:
US20040070028
Pub Dt:
04/15/2004
Title:
METHOD OF FORMING A LOW RESISTANCE SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR
31
Patent #:
7099135
Issue Dt:
08/29/2006
Application #:
10287831
Filing Dt:
11/05/2002
Publication #:
US20040085698
Pub Dt:
05/06/2004
Title:
INTEGRATED INRUSH CURRENT LIMITER CIRCUIT AND METHOD
32
Patent #:
6865063
Issue Dt:
03/08/2005
Application #:
10291015
Filing Dt:
11/12/2002
Publication #:
US20040090726
Pub Dt:
05/13/2004
Title:
INTEGRATED INRUSH CURRENT LIMITER CIRCUIT AND METHOD
33
Patent #:
6809396
Issue Dt:
10/26/2004
Application #:
10303168
Filing Dt:
11/25/2002
Publication #:
US20040099896
Pub Dt:
05/27/2004
Title:
INTEGRATED CIRCUIT WITH VERTICAL PNP TRANSISTOR AND METHOD
34
Patent #:
6984860
Issue Dt:
01/10/2006
Application #:
10305773
Filing Dt:
11/27/2002
Publication #:
US20040099898
Pub Dt:
05/27/2004
Title:
SEMICONDUCTOR DEVICE WITH PARALLEL PLATE TRENCH CAPACITOR AND METHOD
35
Patent #:
6764918
Issue Dt:
07/20/2004
Application #:
10307590
Filing Dt:
12/02/2002
Publication #:
US20040106264
Pub Dt:
06/03/2004
Title:
STRUCTURE AND METHOD OF MAKING A HIGH PERFORMANCE SEMICONDUCTOR DEVICE HAVING A NARROW DOPING PROFILE
36
Patent #:
6870221
Issue Dt:
03/22/2005
Application #:
10313225
Filing Dt:
12/09/2002
Publication #:
US20040108547
Pub Dt:
06/10/2004
Title:
POWER SWITCHING TRANSISTOR WITH LOW DRAIN TO GATE CAPACITANCE
37
Patent #:
6771138
Issue Dt:
08/03/2004
Application #:
10359319
Filing Dt:
02/07/2003
Title:
METHOD OF FORMING A BI-DIRECTIONAL SYNCHRONIZATION CONTROLLER
38
Patent #:
6831516
Issue Dt:
12/14/2004
Application #:
10369230
Filing Dt:
02/20/2003
Publication #:
US20040164802
Pub Dt:
08/26/2004
Title:
METHOD OF FORMING A VARIABLE PROPAGATION DELAY SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR
39
Patent #:
NONE
Issue Dt:
Application #:
10369236
Filing Dt:
02/20/2003
Publication #:
US20040164346
Pub Dt:
08/26/2004
Title:
Power switching transistor with low drain to gate capacitance
40
Patent #:
6812686
Issue Dt:
11/02/2004
Application #:
10369471
Filing Dt:
02/21/2003
Publication #:
US20040166826
Pub Dt:
08/26/2004
Title:
METHOD OF FORMING AN RF DETECTOR AND STRUCTURE THEREFOR
41
Patent #:
6842068
Issue Dt:
01/11/2005
Application #:
10374099
Filing Dt:
02/27/2003
Publication #:
US20040169550
Pub Dt:
09/02/2004
Title:
POWER MANAGEMENT METHOD AND STRUCTURE
42
Patent #:
6833290
Issue Dt:
12/21/2004
Application #:
10374630
Filing Dt:
02/27/2003
Publication #:
US20030201520
Pub Dt:
10/30/2003
Title:
STRUCTURE AND METHOD OF FORMING A MULTIPLE LEADFRAME SEMICONDUCTOR DEVICE
43
Patent #:
7144538
Issue Dt:
12/05/2006
Application #:
10603257
Filing Dt:
06/26/2003
Publication #:
US20040262811
Pub Dt:
12/30/2004
Title:
METHOD FOR MAKING A DIRECT CHIP ATTACH DEVICE AND STRUCTURE
44
Patent #:
6852574
Issue Dt:
02/08/2005
Application #:
10638181
Filing Dt:
08/11/2003
Publication #:
US20050037544
Pub Dt:
02/17/2005
Title:
METHOD OF FORMING A LEADFRAME FOR A SEMICONDUCTOR PACKAGE
45
Patent #:
6982461
Issue Dt:
01/03/2006
Application #:
10729292
Filing Dt:
12/08/2003
Publication #:
US20050127438
Pub Dt:
06/16/2005
Title:
LATERAL FET STRUCTURE WITH IMPROVED BLOCKING VOLTAGE AND ON RESISTANCE PERFORMANCE AND METHOD
46
Patent #:
7109064
Issue Dt:
09/19/2006
Application #:
10729892
Filing Dt:
12/08/2003
Publication #:
US20050127482
Pub Dt:
06/16/2005
Title:
METHOD OF FORMING A SEMICONDUCTOR PACKAGE AND LEADFRAME THEREFOR
47
Patent #:
7189608
Issue Dt:
03/13/2007
Application #:
10741330
Filing Dt:
12/22/2003
Publication #:
US20050136587
Pub Dt:
06/23/2005
Title:
SEMICONDUCTOR DEVICE HAVING REDUCED GATE CHARGE AND REDUCED ON RESISTANCE AND METHOD
48
Patent #:
7098509
Issue Dt:
08/29/2006
Application #:
10750267
Filing Dt:
01/02/2004
Publication #:
US20050145945
Pub Dt:
07/07/2005
Title:
HIGH ENERGY ESD STRUCTURE AND METHOD
49
Patent #:
7052959
Issue Dt:
05/30/2006
Application #:
10752772
Filing Dt:
01/08/2004
Publication #:
US20050153512
Pub Dt:
07/14/2005
Title:
METHOD OF FORMING AN EPROM CELL AND STRUCTURE THEREFOR
50
Patent #:
7087925
Issue Dt:
08/08/2006
Application #:
10773853
Filing Dt:
02/09/2004
Publication #:
US20050173777
Pub Dt:
08/11/2005
Title:
SEMICONDUCTOR DEVICE HAVING REDUCED CAPACITANCE TO SUBSTRATE AND METHOD
51
Patent #:
7126166
Issue Dt:
10/24/2006
Application #:
10797537
Filing Dt:
03/11/2004
Publication #:
US20050218431
Pub Dt:
10/06/2005
Title:
HIGH VOLTAGE LATERAL FET STRUCTURE WITH IMPROVED ON RESISTANCE PERFORMANCE
52
Patent #:
6982574
Issue Dt:
01/03/2006
Application #:
10805405
Filing Dt:
03/22/2004
Publication #:
US20050206436
Pub Dt:
09/22/2005
Title:
METHOD OF FORMING A TRANSISTOR DRIVER AND STRUCTURE THEREFOR
53
Patent #:
6998828
Issue Dt:
02/14/2006
Application #:
10810864
Filing Dt:
03/29/2004
Publication #:
US20050212502
Pub Dt:
09/29/2005
Title:
LOW AUDIBLE NOISE POWER SUPPLY CONTROLLER AND METHOD THEREFOR
54
Patent #:
7034602
Issue Dt:
04/25/2006
Application #:
10811050
Filing Dt:
03/29/2004
Publication #:
US20050212587
Pub Dt:
09/29/2005
Title:
METHOD OF FORMING A FLOATING CHARGE PUMP AND STRUCTURE THEREFOR
55
Patent #:
7157959
Issue Dt:
01/02/2007
Application #:
10813501
Filing Dt:
03/31/2004
Publication #:
US20050218963
Pub Dt:
10/06/2005
Title:
METHOD OF FORMING A SELF-GATED TRANSISTOR AND STRUCTURE THEREFOR
Assignor
1
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Exec Dt:
04/22/2004
Assignee
1
JPMORGAN CHASE BANK, AS COLLATERAL AGENT
270 PARK AVENUE
NEW YORK, NEW YORK 10017
Correspondence name and address
FEDERAL RESEARCH CORPORATION
PENELOPE J.A. AGODOA
1030 FIFTEENTH STREET NW, SUITE 920
WASHINGTON, DC 20005

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