|
Total properties:
32
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/1994
|
Application #:
|
07883113
|
Filing Dt:
|
05/14/1992
|
|
Title:
|
CONDUCTOR TRACK CONFIGURATION FOR VERY LARGE-SCALE INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/1994
|
Application #:
|
08026944
|
Filing Dt:
|
03/05/1993
|
|
Title:
|
FORMATION OF SILICIDED JUNCTIONS IN DEEP SUB-MICRON MOSFETS BY DEFECT ENHANCED COSI2 FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/1996
|
Application #:
|
08235987
|
Filing Dt:
|
05/02/1994
|
|
Title:
|
METHOD FOR THE ANISOTROPIC ETCHING OF AN ALUMINIFEROUS LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/1996
|
Application #:
|
08272589
|
Filing Dt:
|
07/11/1994
|
|
Title:
|
METHOD FOR DEPOSITING A LAYER ON A SUBSTRATE WAFER WITH A SPUTTERING PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/1996
|
Application #:
|
08359789
|
Filing Dt:
|
12/20/1994
|
|
Title:
|
POLYSILICON/POLYCIDE ETCH PROCESS FOR SUB-MICRON GATE STACKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/1997
|
Application #:
|
08362398
|
Filing Dt:
|
12/22/1994
|
|
Title:
|
PLASMA ETCHING METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/1996
|
Application #:
|
08369181
|
Filing Dt:
|
01/05/1995
|
|
Title:
|
CIRCUIT CONFIGURATION FOR PREPARING ANALOG SIGNALS FOR A BOUNDARY SCAN TEST PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/1997
|
Application #:
|
08513494
|
Filing Dt:
|
08/10/1995
|
|
Title:
|
METAL INTERCONNECT STRUCTURE FOR AN INTEGRATED CIRCUIT WITH IMPROVED ELECTROMIGRATION RELIABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/1997
|
Application #:
|
08590931
|
Filing Dt:
|
01/24/1996
|
|
Title:
|
PROTECTIVE CONFIGURATION AGAINST ELECTROSTATIC DISCHARGES IN SEMICONDUCTOR COMPONENTS CONTROLLABLE BY FIELD EFFECT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/1999
|
Application #:
|
08643599
|
Filing Dt:
|
05/06/1996
|
|
Title:
|
METHOD FOR DEPOSITING A SILICON OXIDE LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/1998
|
Application #:
|
08706586
|
Filing Dt:
|
09/05/1996
|
|
Title:
|
ENERGY RELIEVING CRACK STOP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/1998
|
Application #:
|
08744132
|
Filing Dt:
|
11/05/1996
|
|
Title:
|
FORMATION OF SILICIDED JUNCTIONS IN DEEP SUBMICRON MOSFETS BY DEFECT ENHANCED COS12 FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/1999
|
Application #:
|
08753234
|
Filing Dt:
|
11/22/1996
|
|
Title:
|
GEOMETRICAL CONTROL OF DEVICE CORNER THRESHOLD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2001
|
Application #:
|
08756670
|
Filing Dt:
|
11/26/1996
|
|
Title:
|
DISTRIBUTION PLATE FOR A REACTION CHAMBER WITH MULTIPLE GAS INLETS AND SEPARATE MASS FLOW CONTROL LOOPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/1998
|
Application #:
|
08841030
|
Filing Dt:
|
04/29/1997
|
|
Title:
|
METHOD OF MANUFACTURING METAL INTERCONNECT STRUCTURE FOR AN INTEGRATED CIRCUIT WITH IMPROVED ELECTROMIGRATION RELIABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/08/1998
|
Application #:
|
08879727
|
Filing Dt:
|
06/20/1997
|
|
Title:
|
METHODS FOR METAL ETCHING WITH REDUCED SIDEWALL BUILD UP DURING INTEGRATED CIRCUIT MANUFACTURING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/1999
|
Application #:
|
08884119
|
Filing Dt:
|
06/27/1997
|
|
Title:
|
MITIGATION OF CMP-INDUCED BPSG SURFACE DAMAGE BY AN INTEGRATED ANNEAL AND SILICON DIOXIDE DEPOSITION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/1999
|
Application #:
|
08929590
|
Filing Dt:
|
09/15/1997
|
|
Title:
|
METHOD TO MINIMIZE WATERMARKS ON SILICON SUBSTRATES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2000
|
Application #:
|
08937764
|
Filing Dt:
|
09/25/1997
|
|
Title:
|
METHOD OF MAXIMIZING CHIP YIELD FOR SEMICONDUCTOR WAFERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/1999
|
Application #:
|
08940808
|
Filing Dt:
|
09/30/1997
|
|
Title:
|
DISHING RESISTANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2001
|
Application #:
|
08994273
|
Filing Dt:
|
12/19/1997
|
|
Title:
|
METHOD FOR QUANTIFYING PROXIMITY EFFECTS BY MEASURING DEVICE PERFORMANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2000
|
Application #:
|
09004074
|
Filing Dt:
|
01/07/1998
|
|
Title:
|
NON-DESTRUCTIVE METHOD AND DEVICE FOR MEASURING THE DEPTH OF A BURIED INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2000
|
Application #:
|
09007911
|
Filing Dt:
|
01/15/1998
|
|
Title:
|
DUMMY PATTERNS FOR ALUMINUM CHEMICAL POLISHING (CMP)
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2000
|
Application #:
|
09063094
|
Filing Dt:
|
04/21/1998
|
|
Title:
|
HIGH THROUGHPUT A1-CU THIN FILM SPUTTERING PROCESS ON SMALL CONTACT VIA FOR MANUFACTURABLE BEOL WIRING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/1999
|
Application #:
|
09078517
|
Filing Dt:
|
05/15/1998
|
|
Title:
|
GEOMETRICAL CONTROL OF DEVICE CORNER THRESHOLD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2000
|
Application #:
|
09091152
|
Filing Dt:
|
09/02/1998
|
|
Title:
|
CMOS DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2000
|
Application #:
|
09120190
|
Filing Dt:
|
07/22/1998
|
|
Title:
|
GEOMETRICAL CONTROL OF DEVICE CORNER THRESHOLD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2000
|
Application #:
|
09120629
|
Filing Dt:
|
07/22/1998
|
|
Title:
|
PREVENTION OF PHOTORESIST POISONING FROM DIELECTRIC ANTIREFLECTIVE COATING IN SEMICONDUCTOR FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/29/2000
|
Application #:
|
09204402
|
Filing Dt:
|
12/02/1998
|
|
Title:
|
MEASUREMENT SYSTEM AND METHOD FOR MEASURING CRITICAL DIMENSIONS USING ELLIPSOMETRY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2002
|
Application #:
|
09523862
|
Filing Dt:
|
03/14/2000
|
|
Title:
|
DUMMY PATTERNS FOR ALUMINUM CHEMICAL POLISHING (CMP)
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2002
|
Application #:
|
09562217
|
Filing Dt:
|
04/28/2000
|
|
Title:
|
SEMICONDUCTOR DEVICE STRUCTURE WITH HYDROGEN-RICH LAYER FOR FACILITATING PASSIVATION OF SURFACE STATES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2003
|
Application #:
|
09574823
|
Filing Dt:
|
05/19/2000
|
|
Title:
|
WAFER PROCESSING SYSTEM
|
|
