Patent Assignment Details
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| Reel/Frame: | 015393/0017 | |
| Pages: | 3 |
| | Recorded: | 05/24/2004 | | |
| Attorney Dkt #: | 03-2538 81685 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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06/07/2005
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Application #:
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10853637
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Filing Dt:
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05/24/2004
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Title:
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METHOD AND CIRCUIT FOR MATCHING SENSE AMPLIFIER TRIGGER SIGNAL TIMING TO DATA BIT LINE SEPARATION TIMING IN A SELF-TIMED MEMORY ARRAY
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Assignee
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| 1621 BARBER LANE |
| MILPITAS, CALIFORNIA 95035 |
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Correspondence name and address
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LSI LOGIC CORP.
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ERIC J. WHITESELL
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1621 BARBER LANE
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MILPITAS, CA 95035
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