Patent Assignment Details
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| Reel/Frame: | 015437/0357 | |
| Pages: | 4 |
| | Recorded: | 12/10/2004 | | |
| Conveyance: | CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). |
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Total properties:
2
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10758148
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Filing Dt:
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01/14/2004
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Publication #:
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Pub Dt:
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07/14/2005
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Title:
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Efficient use of wafer area with device under the pad approach
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Patent #:
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Issue Dt:
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11/27/2007
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Application #:
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10762445
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Filing Dt:
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01/22/2004
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Publication #:
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Pub Dt:
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07/28/2005
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Title:
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STRUCTURE AND METHOD FOR LOW VSS RESISTANCE AND REDUCED DIBL IN A FLOATING GATE MEMORY CELL
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Assignee
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| ONE AMD PLACE |
| PO BOX 3453, M/S 68 |
| SUNNYVALE, CALIFORNIA 94088-3453 |
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Correspondence name and address
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PAUL S. DRAKE
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ONE AMD PLACE, PO BOX 3453
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MAIL STOP 68
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SUNNYVALE, CA 94088-3453
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