Patent Assignment Details
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| Reel/Frame: | 015624/0351 | |
| Pages: | 5 |
| | Recorded: | 07/22/2004 | | |
| Attorney Dkt #: | 2004p52954usintech30058di |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10896547
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Filing Dt:
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07/22/2004
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Publication #:
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Pub Dt:
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12/23/2004
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Title:
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Extendible process for improved top oxide layer for DRAM array and the gate interconnects while providing self-aligned gate contacts
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Assignee
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| 1730 NORTH FIRST STREET |
| SAN JOSE, CALIFORNIA 95112 |
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Correspondence name and address
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LERNER, DAVID, LITTENBERG, ET AL.
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LAWRENCE E. RUSS
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600 SOUTH AVENUE WEST
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WESTFIELD, NJ 07090
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