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Reel/Frame:015639/0923   Pages: 3
Recorded: 08/02/2004
Attorney Dkt #:03180.0357
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
07/29/2008
Application #:
10801992
Filing Dt:
03/17/2004
Publication #:
Pub Dt:
12/16/2004
Title:
METHOD FOR ANALYZING FAIL BIT MAPS OF WAFERS AND APPARATUS THEREFOR
Assignors
1
Exec Dt:
07/27/2004
2
Exec Dt:
07/27/2004
3
Exec Dt:
07/27/2004
4
Exec Dt:
07/27/2004
Assignee
1
1-1, SHIBAURA 1-CHOME
MINATO-KU, TOKYO, JAPAN
Correspondence name and address
FINNEGAN HENDERSON FARABOW GARRETT &
DUNNER, LLP - MR. ERNEST F. CHAPMAN
1300 I STREET, N.W.
WASHINGTON, D.C. 20005-3315

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