Patent Assignment Details
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| Reel/Frame: | 015678/0110 | |
| Pages: | 2 |
| | Recorded: | 08/13/2004 | | |
| Attorney Dkt #: | 61282-056 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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02/20/2007
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Application #:
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10766954
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Filing Dt:
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01/30/2004
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Publication #:
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Pub Dt:
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12/09/2004
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Title:
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CLOCK DELAY ADJUSTING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FORMED BY THE METHOD
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Assignee
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| 1006, OAZA KADOMA, |
| KADOMA-SHI |
| OSAKA, JAPAN 571-8501 |
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Correspondence name and address
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MCDERMOTT, WILL & EMERY LLP
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RAMYAR M. FARID
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600 13TH STREET, N.W.
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WASHINGTON, DC 20005-3096
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