Total properties:
10
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Patent #:
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Issue Dt:
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10/07/2008
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Application #:
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10028899
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Filing Dt:
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12/20/2001
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Publication #:
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Pub Dt:
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06/26/2003
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Title:
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TASK CONTEXT SWITCHING RTOS
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Patent #:
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Issue Dt:
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03/06/2007
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Application #:
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10881598
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Filing Dt:
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06/30/2004
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Publication #:
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Pub Dt:
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01/05/2006
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Title:
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DIGITAL DUTY CYCLE CORRECTOR
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Patent #:
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Issue Dt:
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08/08/2006
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Application #:
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10898858
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Filing Dt:
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07/26/2004
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Publication #:
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Pub Dt:
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01/26/2006
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Title:
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ENCAPSULATION OF CONDUCTIVE LINES OF SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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05/29/2007
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Application #:
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10899253
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Filing Dt:
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07/26/2004
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Publication #:
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Pub Dt:
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01/26/2006
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Title:
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ALIGNMENT OF MTJ STACK TO CONDUCTIVE LINES IN THE ABSENCE OF TOPOGRAPHY
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Patent #:
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Issue Dt:
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10/28/2008
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Application #:
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10909599
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Filing Dt:
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08/02/2004
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Publication #:
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Pub Dt:
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02/02/2006
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Title:
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DEEP ALIGNMENT MARKS ON EDGE CHIPS FOR SUBSEQUENT ALIGNMENT OF OPAQUE LAYERS
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Patent #:
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Issue Dt:
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01/30/2007
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Application #:
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11046065
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Filing Dt:
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01/28/2005
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Publication #:
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Pub Dt:
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08/03/2006
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Title:
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TEST DATA TOPOLOGY WRITE TO MEMORY USING LATCHED SENSE AMPLIFIER DATA AND ROW ADDRESS SCRAMBLING
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Patent #:
|
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Issue Dt:
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01/02/2007
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Application #:
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11047312
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Filing Dt:
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01/31/2005
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Publication #:
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Pub Dt:
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08/03/2006
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Title:
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SELECTIVE ETCHING TO INCREASE TRENCH SURFACE AREA
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Patent #:
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Issue Dt:
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11/20/2007
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Application #:
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11047928
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Filing Dt:
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02/01/2005
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Publication #:
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Pub Dt:
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08/03/2006
| | | | |
Title:
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SEMICONDUCTOR METHOD AND DEVICE WITH MIXED ORIENTATION SUBSTRATE
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Patent #:
|
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Issue Dt:
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05/22/2007
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Application #:
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11048185
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Filing Dt:
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02/01/2005
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Publication #:
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Pub Dt:
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08/03/2006
| | | | |
Title:
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DUTY CYCLE CORRECTOR
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Patent #:
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NONE
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Issue Dt:
|
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Application #:
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11048186
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Filing Dt:
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02/01/2005
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Publication #:
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Pub Dt:
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08/03/2006
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Title:
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Pillar phase change memory cell
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