Patent Assignment Details
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| Reel/Frame: | 015914/0873 | |
| Pages: | 2 |
| | Recorded: | 10/20/2004 | | |
| Attorney Dkt #: | 1076.1097 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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02/13/2007
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Application #:
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10968110
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Filing Dt:
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10/20/2004
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Publication #:
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Pub Dt:
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01/05/2006
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Title:
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METHOD AND DEVICE FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT AND LOGIC DESIGN PROGRAM
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Assignee
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| 1-1, KAMIKODANAKA, 4-CHOME, NAKAHARA-KU |
| KAWASAKI-SHI, KANAGAWA, JAPAN 211-8588 |
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Correspondence name and address
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STAAS & HALSEY LLP
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DAVID M. PITCHER
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1201 NEW YORK AVENUE, N.W.
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SUITE 700
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WASHINGTON, DC 20005
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