Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 016093/0219 | |
| Pages: | 4 |
| | Recorded: | 06/03/2005 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
4
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Patent #:
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Issue Dt:
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02/06/2007
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Application #:
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10849221
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Filing Dt:
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05/20/2004
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Publication #:
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Pub Dt:
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11/25/2004
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Title:
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METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10910576
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Filing Dt:
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08/04/2004
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Publication #:
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Pub Dt:
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03/10/2005
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Title:
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Transistor structure with gate electrodes having different work functions
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Patent #:
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Issue Dt:
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03/04/2008
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Application #:
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11014884
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Filing Dt:
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12/20/2004
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Publication #:
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Pub Dt:
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06/23/2005
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Title:
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METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING METAL WIRING
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Patent #:
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Issue Dt:
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02/13/2007
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Application #:
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11016890
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Filing Dt:
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12/21/2004
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Publication #:
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Pub Dt:
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06/30/2005
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Title:
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STRUCTURE OF TEST ELEMENT GROUP WIRING AND SEMICONDUCTOR SUBSTRATE
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Assignee
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| 21, SAIIN MIZOSAKI-CHO |
| UKYO-KU |
| KYOTO-SHI, KYOTO, JAPAN 615-8585 |
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Correspondence name and address
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JEFFREY A. WYAND
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700 THIRTEENTH STREET, N. W.
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SUITE 300
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WASHINGTON, DC 20005
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