Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 016207/0606 | |
| Pages: | 4 |
| | Recorded: | 05/09/2005 | | |
| Attorney Dkt #: | 50133.16usu1 / impj-083 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11095938
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Filing Dt:
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03/30/2005
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Publication #:
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Pub Dt:
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10/12/2006
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Title:
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Dual transistor NVM cell with retention-enhanced programmable shared gate logic circuit
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Assignee
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| 501 N. 34TH STREET |
| SUITE 100 |
| SEATTLE, WASHINGTON 98103 |
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Correspondence name and address
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MERCHANT & GOULD PC
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P.O. BOX 2903
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MINNEAPOLIS, MN 55402-0903
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04/29/2024 10:01 AM
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