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Patent Assignment Details
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Reel/Frame:016246/0964   Pages: 5
Recorded: 02/04/2005
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
03/20/2007
Application #:
11049730
Filing Dt:
02/04/2005
Publication #:
Pub Dt:
08/11/2005
Title:
METHOD OF FORMING INTERCONNECTION LINES FOR SEMICONDUCTOR DEVICE
Assignors
1
Exec Dt:
01/21/2005
2
Exec Dt:
01/21/2005
3
Exec Dt:
01/21/2005
4
Exec Dt:
01/21/2005
5
Exec Dt:
01/24/2005
6
Exec Dt:
01/26/2005
Assignee
1
416,MAETAN-DONG,YEONGTONG-GU,SUWON-SI
GYEONGGI-DO, KOREA, REPUBLIC OF
Correspondence name and address
VOLENTINE FRANCOS & WHITT, PLLC
LINUS Y. PARK
11951 FREEDOM DRIVE, SUITE 1260
ONE FREEDOM SQUARE
RESTON, VA 20190

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