Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 016328/0095 | |
| Pages: | 3 |
| | Recorded: | 03/03/2005 | | |
| Conveyance: | RE-RECORD TO CORRECT ASSIGNOR AND ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL/FRAME 015626/0565 |
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Total properties:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10895821
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Filing Dt:
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07/22/2004
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Publication #:
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Pub Dt:
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04/21/2005
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Title:
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Method for processing design data of semiconductor integrated circuit
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Assignee
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| 1006, OAZA KADOMA |
| KADOMA-SHI, OSAKA, JAPAN 571-8501 |
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Correspondence name and address
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MCDERMOTT WILL & EMERY LLP
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600 13TH STREET, N.W.
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WASHINGTON, D.C. 20005-3096
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