Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 016354/0022 | |
| Pages: | 13 |
| | Recorded: | 08/04/2005 | | |
| Conveyance: | PATENT COLLATERAL ASSIGNMENT AND SECURITY INTEREST |
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Total properties:
4
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Patent #:
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Issue Dt:
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03/14/2006
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Application #:
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10242536
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Filing Dt:
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09/11/2002
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Title:
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MEMORY MODULE ASSEMBLY USING PARTIALLY DEFECTIVE CHIPS
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Patent #:
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Issue Dt:
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06/13/2006
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Application #:
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10371663
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Filing Dt:
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02/20/2003
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Publication #:
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Pub Dt:
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08/28/2003
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Title:
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PATCHING METHODS AND APPARATUS FOR FABRICATING MEMORY MODULES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10371736
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Filing Dt:
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02/20/2003
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Publication #:
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Pub Dt:
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08/28/2003
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Title:
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Method and apparatus for implementing a selectively operable clock booster for DDR memory or other logic modules which utilize partially-defective memory parts, or a combination of partially-defective and flawless memory parts
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Patent #:
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Issue Dt:
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07/03/2007
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Application #:
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10371800
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Filing Dt:
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02/20/2003
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Publication #:
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Pub Dt:
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08/28/2003
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Title:
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METHODS AND APPARATUS FOR FABRICATING CHIP-ON-BOARD MODULES
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Assignee
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| 10560 DR. MARTIN LUTHER KING, JR. STREET NORTH |
| ST. PETERSBURG, FLORIDA 33716 |
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Correspondence name and address
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KEVIN A. BUFORD, ESQ.
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1600 TYSONS BOULEVARD
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SUITE 700
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MCLEAN, VA 22102-4867
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