Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 016648/0474 | |
| Pages: | 5 |
| | Recorded: | 08/18/2005 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
|
Total properties:
1
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2007
|
Application #:
|
11184350
|
Filing Dt:
|
07/19/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/25/2007
| | | | |
|
Title:
|
VIA/BSM PATTERN OPTIMIZATION TO REDUCE DC GRADIENTS AND PIN CURRENT DENSITY ON SINGLE AND MULTI-CHIP MODULES
|
|
|
Assignee
|
|
|
|
|
| NEW ORCHARD ROAD |
| ARMONK, NEW YORK 10504 |
|
|
Correspondence name and address
|
| |
CASIMER K. SALYS
|
| |
IBM CORPORATIN
|
| |
INTELLECTUAL PROPERTY LAW
|
| |
11400 BURNET ROAD
|
| |
AUSTIN, TX 78758
|
Search Results as of:
05/13/2024 12:19 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
