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Reel/Frame:017179/0840   Pages: 5
Recorded: 10/31/2005
Attorney Dkt #:sc14359tp
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
08/18/2009
Application #:
11263120
Filing Dt:
10/31/2005
Publication #:
Pub Dt:
05/03/2007
Title:
METHOD FOR FORMING A PLANAR AND VERTICAL SEMICONDUCTOR STRUCTURE HAVING A STRAINED SEMICONDUTOR LAYER
Assignors
1
Exec Dt:
10/24/2005
2
Exec Dt:
10/24/2005
3
Exec Dt:
10/24/2005
4
Exec Dt:
10/24/2005
5
Exec Dt:
10/24/2005
Assignee
1
7700 WEST PARMER LANE
LAW DEPARTMENT
AUSTIN, TEXAS 78729
Correspondence name and address
FREESCALE SEMICONDUCTRO, INC.
MD: TX32/PL02
7700 WEST PARMER LANE
AUSTIN, TX 78729

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