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Patent Assignment Details
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Reel/Frame:017270/0193   Pages: 6
Recorded: 02/16/2006
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
NONE
Issue Dt:
Application #:
11241033
Filing Dt:
09/30/2005
Publication #:
Pub Dt:
04/05/2007
Title:
Method and computer program for analysis of an integrated circuit design to identify and resolve a problematic structure characterized by multiple rule violations using a design closure knowledge base and a physical design database
Assignors
1
Exec Dt:
09/29/2005
2
Exec Dt:
09/29/2005
3
Exec Dt:
09/29/2005
4
Exec Dt:
10/03/2005
5
Exec Dt:
09/29/2005
6
Exec Dt:
09/29/2005
7
Exec Dt:
09/29/2005
8
Exec Dt:
09/30/2005
Assignee
1
1621 BARBER LANE
MILPITAS, CALIFORNIA 95035
Correspondence name and address
LSI LOGIC CORPORATION
1621 BARBER LANE, MS-D-106
MILPITAS, CA 95035

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