Total properties:
13
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Patent #:
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Issue Dt:
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01/23/2001
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Application #:
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09208542
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Filing Dt:
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12/09/1998
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Title:
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LOW TEMPERATURE CVD PROCESSES FOR PREPARING FERROELECTRIC FILMS USING BI AMIDES
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Patent #:
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Issue Dt:
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01/30/2001
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Application #:
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09208543
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Filing Dt:
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12/09/1998
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Title:
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LOW TEMPERATURE CVD PROCESSES FOR PREPARING FERROELECTRIC FILMS USING BI CARBOXYLATES
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Patent #:
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Issue Dt:
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07/25/2006
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Application #:
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10878156
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Filing Dt:
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06/28/2004
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Publication #:
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Pub Dt:
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12/29/2005
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Title:
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TECHNIQUES FOR REDUCING NEEL COUPLING IN TOGGLE SWITCHING SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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05/13/2008
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Application #:
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11189615
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Filing Dt:
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07/26/2005
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Publication #:
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Pub Dt:
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02/01/2007
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Title:
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OUTPUT MATCH TRANSISTOR
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Patent #:
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Issue Dt:
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11/27/2012
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Application #:
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11315069
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Filing Dt:
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12/22/2005
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Publication #:
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Pub Dt:
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06/28/2007
| | | | |
Title:
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SILICON-ON-INSULATOR CHIP HAVING MULTIPLE CRYSTAL ORIENTATIONS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11350191
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Filing Dt:
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02/08/2006
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Publication #:
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Pub Dt:
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08/09/2007
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Title:
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Memory having nanotube transistor access device
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Patent #:
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Issue Dt:
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04/06/2010
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Application #:
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11352047
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Filing Dt:
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02/10/2006
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Publication #:
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Pub Dt:
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08/16/2007
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Title:
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MINIMIZING LOW-K DIELECTRIC DAMAGE DURING PLASMA PROCESSING
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11352565
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Filing Dt:
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02/13/2006
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Publication #:
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Pub Dt:
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08/16/2007
| | | | |
Title:
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Method for fabricating a semiconductor device with a high-K dielectric
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
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11354430
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Filing Dt:
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02/15/2006
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Publication #:
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Pub Dt:
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08/16/2007
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Title:
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Dynamic memory
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Patent #:
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Issue Dt:
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03/16/2010
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Application #:
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11354616
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Filing Dt:
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02/15/2006
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Publication #:
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Pub Dt:
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08/16/2007
| | | | |
Title:
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STRAINED SEMICONDUCTOR DEVICE AND METHOD OF MAKING SAME
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|
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Patent #:
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NONE
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Issue Dt:
|
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Application #:
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11354969
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Filing Dt:
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02/16/2006
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Publication #:
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Pub Dt:
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08/30/2007
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Title:
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Verifying individual probe contact using shared tester channels
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Patent #:
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Issue Dt:
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09/13/2011
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Application #:
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11356666
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Filing Dt:
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02/17/2006
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Publication #:
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Pub Dt:
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08/23/2007
| | | | |
Title:
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CMOS DEVICES HAVING STRESS-ALTERING MATERIAL LINING THE ISOLATION TRENCHES AND METHODS OF MANUFACTURING THEREOF
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Patent #:
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Issue Dt:
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11/18/2008
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Application #:
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11358821
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Filing Dt:
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02/21/2006
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Publication #:
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Pub Dt:
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08/23/2007
| | | | |
Title:
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CONTROL SYSTEM FOR A DYNAMIC RANDOM ACCESS MEMORY AND METHOD OF OPERATION THEREOF
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