Patent Assignment Details
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Reel/Frame: | 017588/0602 | |
| Pages: | 8 |
| | Recorded: | 05/08/2006 | | |
Attorney Dkt #: | 2006 VJ 30279 US |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11343279
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Filing Dt:
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01/30/2006
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Publication #:
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Pub Dt:
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08/02/2007
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Title:
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Memory circuit arrangement and method for reading and/or verifying the status of memory cells of a memory cell array
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Assignees
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ST.-MARTIN-STRASSE 53 |
MUENCHEN, GERMANY 81669 |
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TOPPER BLDG. 65 |
HAMELACHA ST. INDUSTRIAL ZONE SOUTH |
NETANYA, ISRAEL 42504 |
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KOENIGSBRUECKERSTR. 180 |
DRESDEN, GERMANY 01099 |
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Correspondence name and address
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SLATER & MATSIL, L.L.P.
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17950 PRESTON RD.
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SUITE 1000
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DALLAS, TX 75252
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