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Patent Assignment Details
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Reel/Frame:017721/0901   Pages: 2
Recorded: 03/22/2006
Attorney Dkt #:J355-050 US
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
NONE
Issue Dt:
Application #:
10542103
Filing Dt:
03/16/2006
Publication #:
Pub Dt:
09/21/2006
Title:
Calculation processing device, calculation processing device design method, and logic circuit design method
Assignor
1
Exec Dt:
08/22/2005
Assignee
1
902 DAISAN-SYOUMEI-BIRU 18-14, NIHONBASHI 1-CHOME
CHUO-KU, TOKYO, JAPAN 103-0027
Correspondence name and address
NOTARO AND MICHALOS
100 DUTCH HILL ROAD
SUITE 110
ORANGEBURG, NY 10962-2100

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