Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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Reel/Frame: | 017783/0065 | |
| Pages: | 3 |
| | Recorded: | 04/20/2006 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
5
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Patent #:
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Issue Dt:
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09/27/2005
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Application #:
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10410240
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Filing Dt:
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04/09/2003
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Publication #:
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Pub Dt:
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11/27/2003
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Title:
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METHOD OF CONTROLLING INSULATED GATE TRANSISTOR
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Patent #:
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Issue Dt:
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06/09/2009
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Application #:
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11063388
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Filing Dt:
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02/22/2005
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Publication #:
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Pub Dt:
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08/25/2005
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Title:
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HIGH VOLTAGE OPERATING FIELD EFFECT TRANSISTOR, BIAS CIRCUIT THEREFOR AND HIGH VOLTAGE CIRCUIT THEREOF
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Patent #:
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Issue Dt:
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10/07/2008
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Application #:
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11063468
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Filing Dt:
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02/22/2005
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Publication #:
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Pub Dt:
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08/25/2005
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Title:
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HIGH VOLTAGE OPERATING FIELD EFFECT TRANSISTOR, AND BIAS CIRCUIT THEREFOR AND HIGH VOLTAGE CIRCUIT THEREOF
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Patent #:
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Issue Dt:
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01/06/2009
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Application #:
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11092794
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Filing Dt:
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03/29/2005
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Publication #:
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Pub Dt:
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10/06/2005
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Title:
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FLOATING GATE NON-VOLATILE MEMORY
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Patent #:
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Issue Dt:
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03/13/2007
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Application #:
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11121319
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Filing Dt:
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05/03/2005
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Publication #:
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Pub Dt:
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09/08/2005
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Title:
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INSULATED GATE TRANSISTOR
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Assignee
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3-10, UMEZONO 2-CHOME, TSUKUBA-SHI |
IBARAKI, JAPAN 305-0045 |
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Correspondence name and address
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BRUCE L. ADAMS
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ADAMS & WILKS
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17 BATTERY PLACE - SUITE 1231
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NEW YORK, NEW YORK 10004
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