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Total properties:
44
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Patent #:
|
|
Issue Dt:
|
06/27/2000
|
Application #:
|
08401411
|
Filing Dt:
|
03/09/1995
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Title:
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PROCESSOR HAVING A SCALABLE, UNI/MULTI-DIMENSIONAL, AND VIRTUALLY/PHYSICALLY ADDRESSED OPERAND REGISTER FILE
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Patent #:
|
|
Issue Dt:
|
10/12/1999
|
Application #:
|
08440993
|
Filing Dt:
|
05/15/1995
|
|
Title:
|
PROCESSOR HAVING AUXILIARY OPERAND REGISTER FILE AND COMPLEMENTARY ARRANGEMENTS FOR NON-DISRUPTIVELY PERFORMING ADJUNCT EXECUTION
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|
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Patent #:
|
|
Issue Dt:
|
05/04/1999
|
Application #:
|
08528509
|
Filing Dt:
|
09/12/1995
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|
Title:
|
PROCESSOR HAVING A HIERARCHICAL CONTROL REGISTER FILE AND METHODS FOR OPERATING THE SAME
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|
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|
Patent #:
|
|
Issue Dt:
|
11/16/1999
|
Application #:
|
08841415
|
Filing Dt:
|
04/22/1997
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Title:
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APPARATUS AND METHOD FOR COMPUTING THE RESULT OF A VITERBI EQUATION IN A SINGLE CYCLE
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|
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Patent #:
|
|
Issue Dt:
|
11/16/1999
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Application #:
|
08845817
|
Filing Dt:
|
04/29/1997
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|
Title:
|
APPARATUS AND METHOD FOR REVERSING BITS USING A SHIFTER
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|
|
|
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Patent #:
|
|
Issue Dt:
|
07/10/2001
|
Application #:
|
09036403
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Filing Dt:
|
03/05/1998
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|
Title:
|
REGISTER MEMORY LINKING
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2003
|
Application #:
|
09235417
|
Filing Dt:
|
01/20/1999
|
|
Title:
|
CIRCUIT AND METHOD FOR MULTIPLYING AND ACCUMULATING THE SUM OF TWO PRODUCTS IN A SINGLE CYCLE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2003
|
Application #:
|
09467939
|
Filing Dt:
|
12/21/1999
|
|
Title:
|
ALTERNATE BOOTH PARTIAL PRODUCT GENERATION FOR A HARDWARE MULTIPLIER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2004
|
Application #:
|
09847849
|
Filing Dt:
|
04/30/2001
|
|
Title:
|
BRIDGE FOR COUPLING DIGITAL SIGNAL PROCESSOR TO ON-CHIP BUS AS MASTER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2004
|
Application #:
|
09847850
|
Filing Dt:
|
04/30/2001
|
|
Title:
|
BRIDGE FOR COUPLING DIGITAL SIGNAL PROCESSOR TO ON-CHIP BUS AS SLAVE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2005
|
Application #:
|
09901455
|
Filing Dt:
|
07/09/2001
|
|
Title:
|
INCREASING DSP EFFICIENCY BY INDEPENDENT ISSUANCE OF STORE ADDRESS AND DATA
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2005
|
Application #:
|
09924178
|
Filing Dt:
|
08/07/2001
|
|
Title:
|
INSTRUCTION FUSION FOR DIGITAL SIGNAL PROCESSOR
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/01/2005
|
Application #:
|
09972404
|
Filing Dt:
|
10/05/2001
|
|
Title:
|
SYSTEM AND METHOD FOR EXTRACTING INSTRUCTION BOUNDARIES IN A FETCHED CACHELINE, GIVEN AN ARBITRARY OFFSET WITHIN THE CACHELINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2005
|
Application #:
|
09975677
|
Filing Dt:
|
10/11/2001
|
|
Title:
|
INTEGRATED CIRCUIT CONTAINING MULTIPLE DIGITAL SIGNAL PROCESSORS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2007
|
Application #:
|
09993114
|
Filing Dt:
|
11/05/2001
|
|
Title:
|
CONDITIONAL LINK POINTER REGISTER SETS MARKING THE BEGINNING AND END OF A CONDITIONAL INSTRUCTION BLOCK WHERE EACH SET CORRESPONDS TO A SINGLE STAGE OF A PIPELINE THAT MOVES LINK POINTERS THROUGH EACH CORRESPONDING REGISTER OF SAID REGISTER SETS AS INSTRUCTIONS MOVE THROUGH THE PIPELINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2004
|
Application #:
|
09993431
|
Filing Dt:
|
11/05/2001
|
|
Title:
|
EFFICIENT MEMORY MANAGEMENT MECHANISM FOR DIGITAL SIGNAL PROCESSOR AND METHOD OF OPERATION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2006
|
Application #:
|
10002817
|
Filing Dt:
|
11/02/2001
|
|
Title:
|
MECHANISM AND METHOD FOR REDUCING PIPELINE STALLS BETWEEN NESTED CALLS AND DIGITAL SIGNAL PROCESSOR INCORPORATING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2007
|
Application #:
|
10007498
|
Filing Dt:
|
11/13/2001
|
|
Title:
|
PIPELINED MULTIPLY-ACCUMULATE UNIT AND OUT-OF-ORDER COMPLETION LOGIC FOR A SUPERSCALAR DIGITAL SIGNAL PROCESSOR AND METHOD OF OPERATION THEREOF
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2005
|
Application #:
|
10007555
|
Filing Dt:
|
11/08/2001
|
|
Title:
|
MECHANISM FOR SUPPORTING SELF-MODIFYING CODE IN A HARVARD ARCHITECTURE DIGITAL SIGNAL PROCESSOR AND METHOD OF OPERATION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2004
|
Application #:
|
10028898
|
Filing Dt:
|
12/20/2001
|
|
Title:
|
CHANGING INSTRUCTION ORDER BY REASSIGNING ONLY TAGS IN ORDER TAG FIELD IN INSTRUCTION QUEUE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2005
|
Application #:
|
10047515
|
Filing Dt:
|
10/26/2001
|
|
Title:
|
PIPELINE STALL REDUCTION IN WIDE ISSUE PROCESSOR BY PROVIDING MISPREDICT PC QUEUE AND STAGING REGISTERS TO TRACK BRANCH INSTRUCTIONS IN PIPELINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2006
|
Application #:
|
10066147
|
Filing Dt:
|
10/26/2001
|
|
Title:
|
MECHANISM FOR RESOURCE ALLOCATION IN A DIGITAL SIGNAL PROCESSOR BASED ON INSTRUCTION TYPE INFORMATION AND FUNCTIONAL PRIORITY AND METHOD OF OPERATION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2006
|
Application #:
|
10066150
|
Filing Dt:
|
10/26/2001
|
|
Title:
|
EFFICIENT INSTRUCTION PREFETCH MECHANISM EMPLOYING SELECTIVE VALIDITY OF CACHED INSTRUCTIONS FOR DIGITAL SIGNAL PROCESSOR AND METHOD OF OPERATION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2008
|
Application #:
|
10231948
|
Filing Dt:
|
08/30/2002
|
|
Title:
|
SYSTEM AND METHOD FOR EXECUTING SOFTWARE PROGRAM INSTRUCTIONS USING A CONDITION SPECIFIED WITHIN A CONDITIONAL EXECUTION INSTRUCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2006
|
Application #:
|
10256410
|
Filing Dt:
|
09/27/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2004
| | | | |
|
Title:
|
MARKING QUEUE FOR SIMULTANEOUS EXECUTION OF INSTRUCTIONS IN CODE BLOCK SPECIFIED BY CONDITIONAL EXECUTION INSTRUCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2007
|
Application #:
|
10256864
|
Filing Dt:
|
09/27/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2004
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR COOPERATIVE EXECUTION OF MULTIPLE BRANCHING INSTRUCTIONS IN A PROCESSOR
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10262414
|
Filing Dt:
|
09/30/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2004
| | | | |
|
Title:
|
System and method for efficient execution of load/store with update instructions by conditional update of a pointer
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2006
|
Application #:
|
10277339
|
Filing Dt:
|
10/22/2002
|
|
Title:
|
SYSTEM, CIRCUIT, AND METHOD FOR ADJUSTING THE PREFETCH INSTRUCTION RATE OF A PREFETCH UNIT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/22/2005
|
Application #:
|
10277341
|
Filing Dt:
|
10/22/2002
|
|
Title:
|
CIRCUIT AND METHOD FOR IMPROVING INSTRUCTION FETCH TIME FROM A CACHE MEMORY DEVICE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2008
|
Application #:
|
10279344
|
Filing Dt:
|
10/24/2002
|
|
Title:
|
IN-CIRCUIT EMULATION DEBUGGER AND METHOD OF OPERATION THEREOF
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10299532
|
Filing Dt:
|
11/18/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/20/2004
| | | | |
|
Title:
|
Processor having a unified register file with multipurpose registers for storing both address and data register values,a processor having an instruction decoder and an associated register mapping method
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|
|
|
|
Patent #:
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|
Issue Dt:
|
07/26/2005
|
Application #:
|
10310234
|
Filing Dt:
|
12/05/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/10/2004
| | | | |
|
Title:
|
DISTRIBUTED RESULT SYSTEM FOR HIGH-PERFORMANCE WIDE-ISSUE SUPERSCALAR PROCESSOR
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2007
|
Application #:
|
10396265
|
Filing Dt:
|
03/25/2003
|
|
Title:
|
SYSTEM AND METHOD FOR EVALUATING AND EFFICIENTLY EXECUTING CONDITIONAL INSTRUCTIONS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
12/06/2005
|
Application #:
|
10408387
|
Filing Dt:
|
04/07/2003
|
|
Title:
|
SYSTEM AND METHOD FOR REFERENCE-MODELING A PROCESSOR
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2006
|
Application #:
|
10420581
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Filing Dt:
|
04/22/2003
|
|
Publication #:
|
|
Pub Dt:
|
10/28/2004
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR ELECTRICAL POWER MANAGEMENT IN A DATA PROCESSING SYSTEM USING REGISTERS TO REFLECT CURRENT OPERATING CONDITIONS
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|
Patent #:
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|
Issue Dt:
|
07/18/2006
|
Application #:
|
10437485
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Filing Dt:
|
05/14/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/18/2004
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR COOPERATIVE OPERATION OF A PROCESSOR AND COPROCESSOR
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|
|
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|
Patent #:
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|
Issue Dt:
|
05/23/2006
|
Application #:
|
10603303
|
Filing Dt:
|
06/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/30/2004
| | | | |
|
Title:
|
DATA PROCESSING SYSTEMS INCLUDING HIGH PERFORMANCE BUSES AND INTERFACES, AND ASSOCIATED COMMUNICATION METHODS
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|
Patent #:
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|
Issue Dt:
|
01/30/2007
|
Application #:
|
10613128
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Filing Dt:
|
07/03/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/05/2004
| | | | |
|
Title:
|
PROCESSOR AND METHOD FOR CONVOLUTIONAL DECODING
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|
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|
Patent #:
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|
Issue Dt:
|
10/18/2005
|
Application #:
|
10701775
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Filing Dt:
|
11/05/2003
|
|
Title:
|
ASYNCHRONOUS DATA STRUCTURE FOR STORING DATA GENERATED BY A DSP SYSTEM
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|
|
Patent #:
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|
Issue Dt:
|
09/18/2007
|
Application #:
|
10844941
|
Filing Dt:
|
05/13/2004
|
|
Title:
|
HARDWARE LOOPING MECHANISM AND METHOD FOR EFFICIENT EXECUTION OF DISCONTINUITY INSTRUCTIONS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2009
|
Application #:
|
11083575
|
Filing Dt:
|
03/18/2005
|
|
Title:
|
DIGITAL SIGNAL PROCESSOR HAVING INVERSE DISCRETE COSINE TRANSFORM ENGINE FOR VIDEO DECODING AND PARTITIONED DISTRIBUTED ARITHMETIC MULTIPLY/ACCUMULATE UNIT THEREFOR
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|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11222533
|
Filing Dt:
|
09/09/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/15/2007
| | | | |
|
Title:
|
Branch predictor for a processor and method of predicting a conditional branch
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11246595
|
Filing Dt:
|
10/07/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/09/2006
| | | | |
|
Title:
|
Processor implementing conditional execution and including a serial queue
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|
|
|
|
Patent #:
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|
Issue Dt:
|
08/26/2008
|
Application #:
|
11273679
|
Filing Dt:
|
11/14/2005
|
|
Publication #:
|
|
Pub Dt:
|
05/11/2006
| | | | |
|
Title:
|
SIMULTANEOUSLY ASSIGNING CORRESPONDING ENTRY IN MULTIPLE QUEUES OF MULTI-STAGE ENTRIES FOR STORING CONDITION ATTRIBUTES FOR VALIDATING SIMULTANEOUSLY EXECUTED CONDITIONAL EXECUTION INSTRUCTION GROUPS
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