skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:018098/0279   Pages: 4
Recorded: 08/11/2006
Attorney Dkt #:006910.2110 (068354.1573)
Conveyance: CORRECTIVE ASSIGNMENT TO CORRECT THE SECOND ASSIGNOR, PREVIOUSLY RECORDED AT REEL 018062 FRAME 0209.
Total properties: 1
1
Patent #:
Issue Dt:
12/16/2008
Application #:
11421734
Filing Dt:
06/01/2006
Publication #:
Pub Dt:
12/06/2007
Title:
METHOD FOR PROGRAMMING AND ERASING AN ARRAY OF NMOS EEPROM CELLS THAT MINIMIZES BIT DISTURBANCES AND VOLTAGE WITHSTAND REQUIREMENTS FOR THE MEMORY ARRAY AND SUPPORTING CIRCUITS
Assignors
1
Exec Dt:
06/27/2006
2
Exec Dt:
06/27/2006
3
Exec Dt:
06/27/2006
Assignee
1
2355 WEST CHANDLER BLVD.
CHANDLER, ARIZONA 85224-6199
Correspondence name and address
PAUL N. KATZ
BAKER BOTTS L.L.P.
910 LOUISIANA
HOUSTON, TEXAS 77002-4995

Search Results as of: 05/22/2024 06:10 AM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT