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Patent Assignment Details
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Reel/Frame:018264/0299   Pages: 6
Recorded: 09/16/2006
Attorney Dkt #:2004 P 53536 US
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
NONE
Issue Dt:
Application #:
11448169
Filing Dt:
06/06/2006
Publication #:
Pub Dt:
01/11/2007
Title:
Method and system for performing local geometrical operation on a hierarchical layout of a semiconductor device
Assignors
1
Exec Dt:
06/27/2006
2
Exec Dt:
07/05/2006
Assignee
1
ST.-MARTIN-STRASSE 53
MUENCHEN, GERMANY 81669
Correspondence name and address
SLATER & MATSIL, L.L.P.
17950 PRESTON RD., SUITE 1000
DALLAS, TX 75252

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