Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 018313/0990 | |
| Pages: | 4 |
| | Recorded: | 09/28/2006 | | |
| Attorney Dkt #: | T3063-1 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
7
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Patent #:
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Issue Dt:
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12/17/2002
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Application #:
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09906809
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Filing Dt:
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07/18/2001
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Publication #:
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Pub Dt:
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01/31/2002
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Title:
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SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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02/24/2004
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Application #:
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09923405
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Filing Dt:
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08/08/2001
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Publication #:
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Pub Dt:
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02/14/2002
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Title:
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DATA STORING METHOD OF DYNAMIC RAM AND SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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08/12/2003
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Application #:
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09925417
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Filing Dt:
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08/10/2001
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Publication #:
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Pub Dt:
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02/14/2002
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Title:
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SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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09/14/2004
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Application #:
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10041601
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Filing Dt:
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01/10/2002
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Publication #:
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Pub Dt:
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07/18/2002
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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10446734
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Filing Dt:
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05/29/2003
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Publication #:
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Pub Dt:
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11/06/2003
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Title:
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SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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05/23/2006
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Application #:
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10753534
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Filing Dt:
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01/09/2004
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Publication #:
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Pub Dt:
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07/29/2004
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Title:
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DATA STORING METHOD OF DYNAMIC RAM AND SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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01/08/2008
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Application #:
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11399485
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Filing Dt:
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04/07/2006
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Publication #:
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Pub Dt:
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09/07/2006
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Title:
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DATA STORING METHOD OF DYNAMIC RAM AND SEMICONDUCTOR MEMORY DEVICE
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Assignee
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| 2-1, YAESU 2-CHOME |
| CHUO-KU |
| TOKYO, JAPAN |
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Correspondence name and address
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MITCHELL W. SHAPIRO
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1751 PINNACLE DRIVE
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SUITE 500
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MCLEAN, VA 22102
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