Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 018313/0994 | |
| Pages: | 4 |
| | Recorded: | 09/28/2006 | | |
| Attorney Dkt #: | T3063-1 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
4
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Patent #:
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Issue Dt:
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05/31/2005
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Application #:
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10164008
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Filing Dt:
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06/07/2002
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Publication #:
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Pub Dt:
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01/16/2003
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Title:
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INTEGRATED CIRCUIT DEVICE WITH P-TYPE GATE MEMORY CELL HAVING PEDESTAL CONTACT PLUG AND PERIPHERAL CIRCUIT
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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10230107
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Filing Dt:
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08/29/2002
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Publication #:
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Pub Dt:
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03/06/2003
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD WHICH AVOIDS OXIDATION OF SILICON PLUG DURING THERMAL TREATMENT OF CAPACITOR INSULATING FILM
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10352133
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Filing Dt:
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01/28/2003
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Publication #:
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Pub Dt:
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09/18/2003
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH REDUCED LEAKAGE CURRENT CAPACITOR
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10352235
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Filing Dt:
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01/28/2003
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Publication #:
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Pub Dt:
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07/31/2003
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Title:
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Semiconductor integrated circuit device and manufacturing method thereof
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Assignee
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| 2-1, YAESU 2-CHOME |
| CHUO-KU |
| TOKYO, JAPAN |
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Correspondence name and address
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MITCHELL W. SHAPIRO
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1751 PINNACLE DRIVE
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SUITE 500
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MCLEAN, VA 22102
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