Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 018323/0001 | |
| Pages: | 5 |
| | Recorded: | 09/28/2006 | | |
| Attorney Dkt #: | T3063-1 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
5
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Patent #:
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Issue Dt:
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06/18/2002
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Application #:
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09689664
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Filing Dt:
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10/13/2000
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Title:
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SEMICONDUCTOR MEMORY DEVICE OF DDR CONFIGURATION HAVING IMPROVEMENT IN GLITCH IMMUNITY
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Patent #:
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Issue Dt:
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05/11/2004
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Application #:
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09875961
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Filing Dt:
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06/08/2001
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Publication #:
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Pub Dt:
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01/10/2002
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Title:
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METHOD OF DECIDING ERROR RATE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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Patent #:
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Issue Dt:
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01/20/2004
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Application #:
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10120447
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Filing Dt:
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04/12/2002
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Publication #:
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Pub Dt:
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08/29/2002
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Title:
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SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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11/28/2006
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Application #:
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10469819
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Filing Dt:
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09/05/2003
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Publication #:
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Pub Dt:
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04/22/2004
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Title:
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METHOD OF PRODUCING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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Patent #:
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Issue Dt:
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07/24/2007
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Application #:
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10808285
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Filing Dt:
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03/25/2004
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Publication #:
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Pub Dt:
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10/14/2004
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Title:
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METHOD OF DECIDING ERROR RATE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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Assignee
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| 2-1, YAESU 2-CHOME |
| CHUO-KU |
| TOKYO, JAPAN |
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Correspondence name and address
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MITCHELL W. SHAPIRO
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1751 PINNACLE DRIVE
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SUITE 500
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MCLEAN, VA 22102
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