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Patent Assignment Details
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Reel/Frame:018470/0306   Pages: 3
Recorded: 10/27/2006
Attorney Dkt #:04329.3952
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
NONE
Issue Dt:
Application #:
11505917
Filing Dt:
08/18/2006
Publication #:
Pub Dt:
03/01/2007
Title:
Pattern verification method, program thereof, and manufacturing method of semiconductor device
Assignors
1
Exec Dt:
09/04/2006
2
Exec Dt:
09/04/2006
Assignee
1
1-1, SHIBAURA 1-CHOME
MINATO-KU
TOKYO, JAPAN 105-8001
Correspondence name and address
ERNEST F. CHAPMAN
FINNEGAN, HENDERSON, FARABOW, ETAL
901 NEW YORK AVENUE, NW
WASHINGTON, DC 20001-4413

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