Total properties:
433
Page
3
of
5
Pages:
1 2 3 4 5
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/1999
|
Application #:
|
08756518
|
Filing Dt:
|
11/26/1996
|
|
Title:
|
MEMORY DEVICE USING BLOCK WRITE MODE, SIMULTANEOUS COLUMN WRITES WITH COLUMN ADDRESS SELECTION CIRCUIT AND SEGMENT START/STOP ADDRESS LATCHES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/1998
|
Application #:
|
08764105
|
Filing Dt:
|
12/06/1996
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING LDD STRUCTURE WITH POCKET ON DRAIN SIDE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/1998
|
Application #:
|
08769181
|
Filing Dt:
|
12/18/1996
|
|
Title:
|
MEMORY CIRCUIT SEQUENTIALLY ACCESSIBLE BY ARBITRARY ADDRESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/1999
|
Application #:
|
08773615
|
Filing Dt:
|
12/30/1996
|
|
Title:
|
PHOTORESIST CHECK PATTERNS IN HIGHLY INTEGRATED CIRCUITS HAVING MULTI-LEVEL INTERCONNECT LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/1999
|
Application #:
|
08782945
|
Filing Dt:
|
01/13/1997
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING MULTILEVEL WIRING WITH IMPRORED PLANARITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/1997
|
Application #:
|
08788077
|
Filing Dt:
|
01/22/1997
|
|
Title:
|
SERIAL ACCESS MEMORY DEVICE INCLUDING MEMORY SECTIONS HAVING DIFFERENT LATENCIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/1999
|
Application #:
|
08788249
|
Filing Dt:
|
01/27/1997
|
|
Title:
|
SINGLE-CHIP MEMORY SYSTEM HAVING A REDUNDANCY JUDGING CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/1997
|
Application #:
|
08790626
|
Filing Dt:
|
01/29/1997
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/1998
|
Application #:
|
08790800
|
Filing Dt:
|
01/30/1997
|
|
Title:
|
DATA TRANSFER SYSTEM FOR AN INTEGRATED CIRCUIT, CAPABLE OF SHORTENING A DATA TRANSFER CYCLE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/1999
|
Application #:
|
08797340
|
Filing Dt:
|
02/10/1997
|
|
Title:
|
METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING HALF-TONE PHASE SHIFT MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/29/2000
|
Application #:
|
08805229
|
Filing Dt:
|
02/24/1997
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE WITH SIMULTANEOUSLY WRITE CAPABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/1999
|
Application #:
|
08823001
|
Filing Dt:
|
03/21/1997
|
|
Title:
|
VOLTAGE MONITORING CIRCUIT CAPABLE OF REDUCING POWER DISSIPATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/1998
|
Application #:
|
08823688
|
Filing Dt:
|
03/25/1997
|
|
Title:
|
SINGLE-CHIP SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (DRAM) SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/1999
|
Application #:
|
08824085
|
Filing Dt:
|
03/24/1997
|
|
Title:
|
IMPROVEMENT OF BANK SELECTION FOR SYNCHRONOUS READABLE AND WRITABLE SEMICONDUCTOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/1999
|
Application #:
|
08824611
|
Filing Dt:
|
03/27/1997
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE HAVING SHORT READ TIME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/1999
|
Application #:
|
08827730
|
Filing Dt:
|
04/08/1997
|
|
Title:
|
METHOD AND APPARATUS FOR ADJUSTING PHASE OF INTERNAL CLOCK SIGNAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2000
|
Application #:
|
08834036
|
Filing Dt:
|
04/11/1997
|
|
Title:
|
SUBSTRATE POTENTIAL CONTROL CIRCUIT CAPABLE OF MAKING A SUBSTRATE POTENTIAL CHANGE IN RESPONSE TO A POWER-SUPPLY VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/1999
|
Application #:
|
08834294
|
Filing Dt:
|
04/15/1997
|
|
Title:
|
DYNAMIC MEMORY DEVICE WITH CIRCUITS FOR SETTING SELF-REFRESHING PERIOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/1998
|
Application #:
|
08837953
|
Filing Dt:
|
04/28/1997
|
|
Title:
|
SEMICONDUCTOR MEMORY IC TESTING DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/1998
|
Application #:
|
08855535
|
Filing Dt:
|
05/13/1997
|
|
Title:
|
CONTROLLED DELAY CIRCUIT FOR USE IN SYNCHRONIZED SEMICONDUCTOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/1999
|
Application #:
|
08856802
|
Filing Dt:
|
05/15/1997
|
|
Title:
|
SEMICONDUCTOR DEVICE CAPABLE OF DECREASING AN INTERNAL VOLTAGE IN PERIOD OF ACCELERATION TEST
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/1999
|
Application #:
|
08857443
|
Filing Dt:
|
05/16/1997
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING TWO OR MORE BONDING OPTION PADS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/1998
|
Application #:
|
08857828
|
Filing Dt:
|
05/16/1997
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING A LATCH CIRCUIT FOR LATCHING DATA EXTERNALLY INPUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/1999
|
Application #:
|
08859715
|
Filing Dt:
|
05/21/1997
|
|
Title:
|
READ BUS CONTROLLING APPARATUS FOR SEMICONDUCTOR STORAGE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/1999
|
Application #:
|
08876293
|
Filing Dt:
|
06/16/1997
|
|
Title:
|
REDUNDANT DECODER UTILIZING ADDRESS SIGNAL AND BURST LENGTH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2000
|
Application #:
|
08880989
|
Filing Dt:
|
06/23/1997
|
|
Title:
|
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/1999
|
Application #:
|
08884262
|
Filing Dt:
|
06/27/1997
|
|
Title:
|
CAPACITOR DESIGNING METHOD OF MOS TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1999
|
Application #:
|
08886463
|
Filing Dt:
|
07/01/1997
|
|
Title:
|
LOGICAL CIRCUIT CAPABLE OF UNIFORMIZING OUTPUT DELAYS FOR DIFFERENT INPUTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/1999
|
Application #:
|
08890943
|
Filing Dt:
|
07/10/1997
|
|
Title:
|
SEMICONDUCTOR MEMORY AND A COLUMN REDUNDANCY DISCRIMINATION CIRCUIT APPLIED THEREIN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/1999
|
Application #:
|
08891196
|
Filing Dt:
|
07/10/1997
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/1998
|
Application #:
|
08892029
|
Filing Dt:
|
07/14/1997
|
|
Title:
|
SEMICONDUCTOR MEMORY HAVING REDUNDANCY FUNCTION IN BLOCK WRITE OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/1999
|
Application #:
|
08893568
|
Filing Dt:
|
07/11/1997
|
|
Title:
|
RANDOM ACCESS MEMORY WITH PLURAL SIMULTANEOUSLY OPERABLE BANKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/1999
|
Application #:
|
08895593
|
Filing Dt:
|
07/16/1997
|
|
Title:
|
SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/1999
|
Application #:
|
08898344
|
Filing Dt:
|
07/22/1997
|
|
Title:
|
SEMICONDUCTOR PROTECTION DEVICE FORMED INSIDE A WELL HAVING CONTACT WITH A BURIED LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2000
|
Application #:
|
08903375
|
Filing Dt:
|
07/30/1997
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING REDUNDANT MEMORY CELL ARRAYS AND SERIALLY ACCESSING ADDRESSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1999
|
Application #:
|
08904917
|
Filing Dt:
|
08/01/1997
|
|
Title:
|
SEMICONDUCTOR CIRCUIT DEVICE WITH HIGH ELECTROSTATIC BREAKDOWN ENDURANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/1999
|
Application #:
|
08906336
|
Filing Dt:
|
08/05/1997
|
|
Title:
|
MOSFET FOR INPUT/OUTPUT PROTECTIVE CIRCUIT HAVING A MULTI-LAYERED CONTACT STRUCTURE WITH MULTIPLE CONTACT HOLES ON A SINGLE DIFFUSION LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/1999
|
Application #:
|
08907946
|
Filing Dt:
|
08/11/1997
|
|
Title:
|
SYNCHRONOUS SEMICONDUCTOR MEMORY HAVING A REDUCED NUMBER OF REGISTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/1998
|
Application #:
|
08908058
|
Filing Dt:
|
08/11/1997
|
|
Title:
|
METHOD OF PREPROGRAMMING BEFORE VERIFYING IN NON-VOLATILE MEMORY DEVICE AND APPARATUS FOR THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2000
|
Application #:
|
08908517
|
Filing Dt:
|
08/07/1997
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE WITH HIGH SPEED READ-MODIFY-WRITE FUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/1998
|
Application #:
|
08908709
|
Filing Dt:
|
08/08/1997
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE HAVING REDUNDANT DECODER WITH SUBTANTIALLY CONSTANT MARGIN REGARDLESS OF POWER VOLTAGE LEVEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/1999
|
Application #:
|
08908710
|
Filing Dt:
|
08/08/1997
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE HAVING A BIT COMPRESSED TEST MODE AND A CHECK MODE SELECTING SECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/1999
|
Application #:
|
08914236
|
Filing Dt:
|
08/20/1997
|
|
Title:
|
SEMICONDUCTOR DEVICE WITH BOOT-STRAP OUTPUT CIRCUIT AND CLAMPING CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2000
|
Application #:
|
08916061
|
Filing Dt:
|
08/21/1997
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING A MULTI-WALL CYLINDRICAL CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/1999
|
Application #:
|
08921329
|
Filing Dt:
|
08/29/1997
|
|
Title:
|
SEMICONDUCTOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/1998
|
Application #:
|
08922665
|
Filing Dt:
|
09/03/1997
|
|
Title:
|
GUIDANCE SYSTEM FOR AUTOMATED GUIDED VEHICLE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/1999
|
Application #:
|
08936605
|
Filing Dt:
|
09/24/1997
|
|
Title:
|
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/1999
|
Application #:
|
08940763
|
Filing Dt:
|
09/30/1997
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING AN INSULATED GATE FIELD EFFECT TRANSISTOR AND A W ELL SPACED FROM THE CANANNEL REGION OF THE INSULATED GATE FIELD EFFECT TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2000
|
Application #:
|
08942299
|
Filing Dt:
|
10/01/1997
|
|
Title:
|
SINGLE -CHIP DYNAMIC RANDOM ACCESS MEMORY (DRAM) SYSTEM AND METHOD FOR OPERATING THE SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/1998
|
Application #:
|
08946355
|
Filing Dt:
|
10/07/1997
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/1998
|
Application #:
|
08951412
|
Filing Dt:
|
10/16/1997
|
|
Title:
|
SEMICONDUCTOR DEVICE EQUIPPED WITH ELECTROSTATIC BREAKDOWN PROTECTION CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2000
|
Application #:
|
08954098
|
Filing Dt:
|
10/20/1997
|
|
Title:
|
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH RESTORING CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/1999
|
Application #:
|
08956369
|
Filing Dt:
|
10/23/1997
|
|
Title:
|
SINGLE-CHIP MEMORY SYSTEM AND METHOD FOR OPERATING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/1999
|
Application #:
|
08956681
|
Filing Dt:
|
10/23/1997
|
|
Title:
|
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING A PEAK CONCENTRATION THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2000
|
Application #:
|
08960217
|
Filing Dt:
|
10/29/1997
|
|
Title:
|
CHIP-LEAD INTERCONNECTION STRUCTURE IN A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/1999
|
Application #:
|
08969340
|
Filing Dt:
|
11/28/1997
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/1999
|
Application #:
|
08969341
|
Filing Dt:
|
11/28/1997
|
|
Title:
|
SINGLE-CHIP SYSTEM HAVING ELECTROSTATIC DISCHARGE (ESD) PROTECTIVE CIRCUITRY INCLUDING A SINGLE BIPOLAR TRANSISTOR PORTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/1999
|
Application #:
|
08971747
|
Filing Dt:
|
11/17/1997
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE WITH PERIPHERAL DUMMY CELL ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2001
|
Application #:
|
08979685
|
Filing Dt:
|
11/26/1997
|
|
Title:
|
WIRING STRUCTURE WITH DIVIDED WIRING CONDUCTORS TO ACHIEVE PLANARITY IN AN OVERLYING SOG LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2000
|
Application #:
|
08980281
|
Filing Dt:
|
11/28/1997
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING AN IMPROVED THROUGH-HOLE STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/1999
|
Application #:
|
08995973
|
Filing Dt:
|
12/22/1997
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/1999
|
Application #:
|
09008576
|
Filing Dt:
|
01/16/1998
|
|
Title:
|
SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE CAPABLE OF IMPROVING LOAD OF CLOCK SIGNAL LINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2000
|
Application #:
|
09012189
|
Filing Dt:
|
01/23/1998
|
|
Title:
|
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE PRODUCED FROM MASTER SLICE AND HAVING OPERATION MODE EASILY CHANGEABLE AFTER SELECTION ON MASTER SLICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/1999
|
Application #:
|
09017470
|
Filing Dt:
|
02/02/1998
|
|
Title:
|
A SEMICONDUCTOR MEMORY DEVICE WITH WRITE-SWITCH SIGNAL OUTPUT CIRCUITS USING COMPLEMENTARY WRITE DATA SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2000
|
Application #:
|
09019505
|
Filing Dt:
|
02/06/1998
|
|
Title:
|
MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2001
|
Application #:
|
09019707
|
Filing Dt:
|
02/06/1998
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING A THROUGH-HOLE OF A TWO-LEVEL STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/1999
|
Application #:
|
09019737
|
Filing Dt:
|
02/06/1998
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING OPENING PORTION FOR FUSE BREAKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/1999
|
Application #:
|
09025154
|
Filing Dt:
|
02/18/1998
|
|
Title:
|
STATIC RAM HAVING A STABLE HIGH-RESISTANCE LOAD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/1999
|
Application #:
|
09035964
|
Filing Dt:
|
03/06/1998
|
|
Title:
|
SEMICONDUCTOR ELEMENT STRUCTURE WITH STEPPED PORTION FOR FORMATION OF ELEMENT PATTERNS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2000
|
Application #:
|
09046620
|
Filing Dt:
|
03/24/1998
|
|
Title:
|
RANDOM ACCESS MEMORY WITH SEPARATE ROW AND COLUMN DESIGNATION CIRCUITS FOR READING AND WRITING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/1999
|
Application #:
|
09058772
|
Filing Dt:
|
04/13/1998
|
|
Title:
|
HORIZONTAL PACKAGE HAVING DIE SUPPORTS LEADS FORMED ALONG LEAD COLUMN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2000
|
Application #:
|
09059260
|
Filing Dt:
|
04/14/1998
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/1999
|
Application #:
|
09064504
|
Filing Dt:
|
04/23/1998
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/1999
|
Application #:
|
09079548
|
Filing Dt:
|
05/15/1998
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING A LATCH CIRCUIT FOR LATCHING DATA EXTERNALLY INPUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/1999
|
Application #:
|
09085059
|
Filing Dt:
|
05/27/1998
|
|
Title:
|
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING CONFIRMABLE SELF-DIAGNOSTIC FUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2000
|
Application #:
|
09086066
|
Filing Dt:
|
05/29/1998
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE WITH INDEPENDENTLY OPERATING MEMORY BANKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/1999
|
Application #:
|
09092041
|
Filing Dt:
|
06/05/1998
|
|
Title:
|
METHOD FOR PRODUCING DYNAMIC RAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2000
|
Application #:
|
09093339
|
Filing Dt:
|
06/09/1998
|
|
Title:
|
SEMICONDUCTOR SYNCHRONOUS PIPELINE MEMORY HAVING DATA AMPLIFIERS SELECTIVELY SUPPLIED WITH DATA SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2001
|
Application #:
|
09097667
|
Filing Dt:
|
06/16/1998
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING WIRING DETOUR AROUND STEP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/1999
|
Application #:
|
09098339
|
Filing Dt:
|
06/17/1998
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE USING SENSE AMPLIFIERS IN A DUMMY CELL AREA FOR INCREASING WRITING SPEED
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/1999
|
Application #:
|
09098376
|
Filing Dt:
|
06/17/1998
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE WITH INPUT/OUTPUT MASKING FUNCTION WITHOUT DESTRUCTION OF DATA BIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2000
|
Application #:
|
09099406
|
Filing Dt:
|
06/18/1998
|
|
Title:
|
ESD PROTECTION CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2001
|
Application #:
|
09102638
|
Filing Dt:
|
06/23/1998
|
|
Title:
|
MEMORY MODULE HAVING RANDOM ACCESS MEMORIES WITH DEFECTIVE ADDRESSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2000
|
Application #:
|
09106266
|
Filing Dt:
|
06/29/1998
|
|
Title:
|
REFERENCE VOLTAGE GENERATING CIRCUIT OF GENERATING A PLURALITY OF REFERENCE VOLTAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/1999
|
Application #:
|
09107501
|
Filing Dt:
|
06/30/1998
|
|
Title:
|
VOLTAGE STEP-UP CIRCUIT AND METHOD FOR CONTROLLING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2000
|
Application #:
|
09107502
|
Filing Dt:
|
06/30/1998
|
|
Title:
|
DIFFERENTIAL AMPLIFIER HAVING A REDUCED CURRENT DISSIPATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09114940
|
Filing Dt:
|
07/14/1998
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/1999
|
Application #:
|
09120507
|
Filing Dt:
|
07/23/1998
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE HAVING BURN-IN TEST FUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2000
|
Application #:
|
09120737
|
Filing Dt:
|
07/23/1998
|
|
Title:
|
RING OSCILLATOR GENERATING PULSE SIGNAL AT CONSTANT PULSE PERIOD UNDER UNSTABLE POWER VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/1999
|
Application #:
|
09120738
|
Filing Dt:
|
07/23/1998
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE HAVING A SAVE REGISTER FOR READ DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2000
|
Application #:
|
09124769
|
Filing Dt:
|
07/30/1998
|
|
Title:
|
CLOCK SIGNAL GENERATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2000
|
Application #:
|
09131198
|
Filing Dt:
|
08/07/1998
|
|
Title:
|
SYNCHRONOUS-TYPE SEMICONDUCTOR STORAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/1999
|
Application #:
|
09132824
|
Filing Dt:
|
08/12/1998
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/1999
|
Application #:
|
09134158
|
Filing Dt:
|
08/14/1998
|
|
Title:
|
NNPUT INTERFACE LEVEL DETERMINER FOR USE IN A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1999
|
Application #:
|
09138010
|
Filing Dt:
|
08/21/1998
|
|
Title:
|
IMPROVED DEFECTIVE MEMORY CELL ADDRESS DETECTING CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2003
|
Application #:
|
09141300
|
Filing Dt:
|
08/27/1998
|
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD WITH IMPROVED FLAT SURFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2000
|
Application #:
|
09149112
|
Filing Dt:
|
09/09/1998
|
|
Title:
|
SEMICONDUCTOR DEVICE WITH PROTECTION CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2001
|
Application #:
|
09149115
|
Filing Dt:
|
09/09/1998
|
|
Title:
|
SEMICONDUCTOR INTEGRATED CIRCUIT WITH PROTECTION CIRCUIT AGAINST ELECT ROSTATIC DISCHARGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09162787
|
Filing Dt:
|
09/30/1998
|
|
Title:
|
SEMICONDUCTOR DEVICE AND PRODUCING METHOD THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/1999
|
Application #:
|
09179853
|
Filing Dt:
|
10/28/1998
|
|
Title:
|
SEMICONDUCTOR STORAGE APPARATUS HAVING AN ACTIVATION SIGNAL GENERATING CIRCUITRY DISPOSED BOTH ON THE INSIDE AND IN BETWEEN THE SENSE AMPLIFIER AREAS
|
|
