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Patent #:
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Issue Dt:
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03/21/2000
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Application #:
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09010217
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Filing Dt:
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01/21/1998
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Title:
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CACHE BASED SCAN MATRIX KEYBOARD CONTROLLER
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Patent #:
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Issue Dt:
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07/04/2000
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Application #:
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09010897
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Filing Dt:
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01/22/1998
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Title:
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HIGH-SPEED MODULAR EXPONENTIATOR AND MULTIPLIER
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Patent #:
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Issue Dt:
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06/06/2000
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Application #:
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09013584
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Filing Dt:
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01/27/1998
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Title:
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SYSTEM HAVING PROCESSOR MONITORING CAPABILITY OF AN INTEGRATED CIRCUITS BURIED INTERNAL BUS FOR USE WITH A PLURALITY OF INTERNAL MASTERS AND A METHOD THEREFOR
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Patent #:
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Issue Dt:
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03/13/2001
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Application #:
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09014008
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Filing Dt:
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01/27/1998
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Title:
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SYSTEM AND METHOD FOR ACCESSING INFORMATION DECRYPTED IN MULTIPLE -BYTE BLOCKS
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Patent #:
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Issue Dt:
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03/30/1999
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Application #:
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09014832
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Filing Dt:
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01/28/1998
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Title:
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MICRO-ELECTROMECHANICAL VOLTAGE SHIFTER
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Patent #:
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Issue Dt:
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11/21/2000
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Application #:
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09015328
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Filing Dt:
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01/29/1998
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Title:
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FIVE VOLT TOLERANT I/O BUFFER
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Patent #:
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Issue Dt:
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04/11/2000
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Application #:
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09016752
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Filing Dt:
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01/30/1998
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Title:
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AUTOCLAVE WITH IMPROVED HEATING AND ACCESS
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Patent #:
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Issue Dt:
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06/05/2001
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Application #:
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09023638
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Filing Dt:
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02/13/1998
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Title:
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SYSTEM FOR DISLODGING BY-PRODUCT AGGLOMERATIONS FROM A POLISHING PAD OF A CHEMICAL MECHANICAL POLISHING MACHINE
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Patent #:
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Issue Dt:
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03/07/2000
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Application #:
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09024967
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Filing Dt:
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02/06/1998
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Title:
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OPTIMIZED UNDERLAYER STRUCTURES FOR MAINTAINING CHEMICAL MECHANICAL POLISHING REMOVAL RATES
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Patent #:
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Issue Dt:
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07/18/2000
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Application #:
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09025020
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Filing Dt:
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02/17/1998
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Title:
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SELECTIVE DATA READ-AHEAD IN BUS-TO-BUS BRIDGE ARCHITECTURE
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Patent #:
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Issue Dt:
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07/18/2000
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Application #:
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09025215
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Filing Dt:
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02/18/1998
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Title:
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PROTECTION CIRCUITS AND METHODS OF PROTECTING A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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02/29/2000
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Application #:
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09025429
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Filing Dt:
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02/18/1998
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Title:
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METHODS OF PROTECTING A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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08/07/2001
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Application #:
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09028857
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Filing Dt:
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02/24/1998
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Title:
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PROGRAMMABLE DELAY PATH CIRCUIT AND OPERATING POINT FREQUENCY DETECTION APPARATUS
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Patent #:
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Issue Dt:
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07/25/2000
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Application #:
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09031169
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Filing Dt:
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02/26/1998
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Title:
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METHOD OF MINIMIZING DISHING DURING CHEMICAL MECHANICAL POLISHING OF SEMICONDUCTOR METALS FOR MAKING A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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10/16/2001
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Application #:
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09031364
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Filing Dt:
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02/26/1998
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Title:
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METHOD OF IMPROVING PROCESS ROBUSTNESS OF NICKEL SALICIDE IN SEMICONDUCTORS
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Patent #:
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Issue Dt:
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06/27/2000
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Application #:
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09041892
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Filing Dt:
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03/12/1998
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Title:
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ADDRESS DEPENDENT RETRY SYSTEM TO PROGRAM THE RETRY LATENCY OF AN INITIATOR PCI AGENT
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Patent #:
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Issue Dt:
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03/26/2002
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Application #:
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09042605
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Filing Dt:
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03/16/1998
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Publication #:
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Pub Dt:
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08/02/2001
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Title:
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METHOD OF PROTECTING QUARTZ HARDWARE FROM ETCHING DURING PLASMA-ENHANCED CLEANING OF A SEMICONDUCTOR PROCESSING CHAMBER
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Patent #:
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Issue Dt:
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10/17/2000
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Application #:
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09045469
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Filing Dt:
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03/20/1998
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Title:
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METHOD OF AND SYSTEM FOR ALLOWING A COMPUTER SYSTEM TO ACCESS CACHEABLE MEMORY IN A NON-CACHEABLE MANNER
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Patent #:
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Issue Dt:
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01/11/2000
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Application #:
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09052859
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Filing Dt:
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03/31/1998
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Title:
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SEMICONDUCTOR STRUCTURES FOR SUPPRESSING GATE OXIDE PLASMA CHARGING DAMAGE AND METHODS FOR MAKING THE SAME
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Patent #:
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Issue Dt:
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01/04/2000
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Application #:
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09052865
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Filing Dt:
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03/31/1998
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Title:
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METHODS FOR MAKING SHALLOW TRENCH CAPACITIVE STRUCTURES
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Patent #:
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Issue Dt:
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02/01/2000
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Application #:
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09052908
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Filing Dt:
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03/31/1998
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Title:
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AUTOMATED DESIGN OF ON-CHIP CAPACITIVE STRUCTURES FOR SUPPRESSING INDUCTIVE NOISE
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Patent #:
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Issue Dt:
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09/07/1999
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Application #:
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09054937
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Filing Dt:
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04/03/1998
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Title:
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PRODUCTION AND TEST SOCKET FOR BALL GRID ARRAY SEMICONDUCTOR PACKAGE
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Patent #:
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Issue Dt:
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03/16/1999
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Application #:
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09055018
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Filing Dt:
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04/03/1998
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Title:
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LOW POWER PROGRAMMABLE FUSE STRUCTURES AND METHODS FOR MAKING THE SAME
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Patent #:
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Issue Dt:
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11/30/1999
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Application #:
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09059631
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Filing Dt:
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04/13/1998
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Title:
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PSEUDO-DIFFERENTIAL LOGIC RECEIVER
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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09061820
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Filing Dt:
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04/16/1998
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Title:
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RECURSIVE LOOKAHEAD-BASED 2N-BIT SERIAL MULTIPLIERS OVER GALOIS FIELD GF (2M)
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Patent #:
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Issue Dt:
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05/16/2000
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Application #:
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09064014
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Filing Dt:
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04/20/1998
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Title:
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METHOD FOR ADAPTIVE SAMPLING FOR BUILDING ACCURATE COMPUTER MODELS
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Patent #:
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Issue Dt:
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12/19/2000
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Application #:
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09073734
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Filing Dt:
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05/06/1998
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Title:
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METHOD FOR SUBSTANTIALLY PREVENTING FOOTINGS IN CHEMICALLY AMPLIFIED DEEP ULTRA VIOLET PHOTORESIST LAYERS
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Patent #:
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Issue Dt:
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04/24/2001
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Application #:
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09074564
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Filing Dt:
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05/07/1998
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Title:
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INTEGRATED CIRCUIT DEVICE WITH INTEGRAL DECOUPLING CAPACITOR
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Patent #:
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Issue Dt:
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07/11/2000
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Application #:
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09075847
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Filing Dt:
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05/12/1998
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Title:
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LOGIC SYNTHESIS CONSTRAINTS ALLOCATION AUTOMATING THE CONCURRENT ENGINEERING FLOWS
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Patent #:
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Issue Dt:
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11/23/1999
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Application #:
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09076574
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Filing Dt:
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05/11/1998
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Title:
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SYSTEM INCLUDING ESD PROTECTION
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Patent #:
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Issue Dt:
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04/23/2002
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Application #:
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09079990
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Filing Dt:
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05/14/1998
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Title:
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OPTIMIZED CPU-MEMORY HIGH BANDWIDTH MULTIBUS STRUCTURE SIMULTANEOUSLY SUPPORTING DESIGN REUSABLE BLOCKS
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Patent #:
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Issue Dt:
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10/31/2000
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Application #:
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09083251
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Filing Dt:
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05/21/1998
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Title:
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SEMICONDUCTOR DEVICE HAVING LOAD DEVICE WITH TRENCH ISOLATION REGION AND FABRICATION THEREOF
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Patent #:
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Issue Dt:
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08/15/2000
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Application #:
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09086700
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Filing Dt:
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05/28/1998
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Title:
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METHOD FOR REDUCING FACETING ON A PHOTORESIST LAYER DURING AN ETCH PROCESS
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Patent #:
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Issue Dt:
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12/12/2000
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Application #:
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09087492
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Filing Dt:
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05/29/1998
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Title:
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FABRICATION OF GATE AND DIFFUSION CONTACTS IN SELF-ALIGNED CONTACT PROCESS
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Patent #:
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Issue Dt:
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03/13/2001
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Application #:
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09095729
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Filing Dt:
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06/10/1998
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Title:
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SMART DEBUG INTERFACE CIRCUIT
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Patent #:
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Issue Dt:
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04/24/2001
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Application #:
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09100639
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Filing Dt:
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06/19/1998
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Title:
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METHOD FOR FORMING ALIGNED VIAS UNDER TRENCHES IN A DUAL DAMASCENE PROCESS
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Patent #:
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Issue Dt:
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12/05/2000
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Application #:
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09102367
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Filing Dt:
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06/23/1998
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Title:
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METHOD OF FORMING ANTI-FUSE STRUCTURE
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Patent #:
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Issue Dt:
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10/02/2001
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Application #:
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09102797
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Filing Dt:
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06/23/1998
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Title:
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SACRIFICIAL MULTILAYER ANTI-REFLECTIVE COATING FOR MOS GATE FORMATION
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Patent #:
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Issue Dt:
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06/12/2001
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Application #:
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09103439
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Filing Dt:
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06/24/1998
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Title:
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DIGITAL REVERBERATION PROCESSOR AND METHOD FOR GENERATING DIGITAL REVERBERATION
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Patent #:
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Issue Dt:
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03/12/2002
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Application #:
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09103642
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Filing Dt:
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06/23/1998
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Title:
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SYSTEM TO AVOID UNSTABLE DATA TRANSFER BETWEEN DIGITAL SYSTEMS
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Patent #:
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Issue Dt:
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04/25/2000
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Application #:
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09104753
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Filing Dt:
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06/25/1998
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Title:
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METHOD FOR ENCAPSULATING A METAL VIA IN DAMASCENE
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Patent #:
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Issue Dt:
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04/03/2001
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Application #:
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09105285
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Filing Dt:
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06/26/1998
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Title:
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SECURE DATA COMMUNICATION OVER A MEMORY-MAPPED SERIAL COMMUNICATIONS INTERFACE UTILIZING A DISTRIBUTED FIREWALL
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Patent #:
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Issue Dt:
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10/17/2000
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Application #:
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09105553
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Filing Dt:
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06/26/1998
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Title:
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PHYSICAL LAYER SECURITY MANAGER FOR MEMORY-MAPPED SERIAL COMMUNICATIONS INTERFACE
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Patent #:
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Issue Dt:
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04/03/2001
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Application #:
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09106718
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Filing Dt:
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06/29/1998
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Title:
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CHEMICAL WET ETCH REMOVAL OF UNDERLAYER MATERIAL AFTER PERFORMING CHEMICAL MECHANICAL POLISHING ON A PRIMARY LAYER
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Patent #:
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Issue Dt:
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05/23/2000
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Application #:
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09106719
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Filing Dt:
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06/29/1998
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Title:
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LOW POWER PLUG-IN CARD REMOVAL DETECTION
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Patent #:
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Issue Dt:
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09/11/2001
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Application #:
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09107024
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Filing Dt:
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06/29/1998
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Title:
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MEMORY CONFIGURATION WHICH SUPPORT MULTIPLE CRYTOGRAPHICAL ALGORITHMS
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09107030
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Filing Dt:
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06/29/1998
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Title:
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DUAL POINTER CIRCULAR QUEUE
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Patent #:
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Issue Dt:
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03/13/2001
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Application #:
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09109848
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Filing Dt:
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07/02/1998
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Title:
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ANALOG TEST ACCESS PORT AND METHOD THEREFOR
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Patent #:
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Issue Dt:
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09/12/2000
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Application #:
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09110872
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Filing Dt:
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07/07/1998
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Title:
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METHOD AND APPARATUS FOR READING MULTIPLE MATCHED ADDRESSES
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Patent #:
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Issue Dt:
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08/29/2000
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Application #:
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09115714
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Filing Dt:
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07/15/1998
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Title:
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SEMICONDUCTOR DEVICE WITH GATE ELECTRODES FOR SUB-MICRON APPLICATIONS AND FABRICATION THEREOF
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Patent #:
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Issue Dt:
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05/16/2000
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Application #:
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09119081
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Filing Dt:
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07/20/1998
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Title:
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HOT DOCKING SYSTEM FOR DETECTING AND MANAGING HOT DOCKING OF BUS CARDS
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Patent #:
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Issue Dt:
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12/14/1999
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Application #:
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09120895
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Filing Dt:
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07/22/1998
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Title:
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PROCESS TO IMPROVE ADHESION OF CAP LAYERS IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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10/16/2001
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Application #:
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09121180
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Filing Dt:
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07/22/1998
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Title:
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PROCESS TO IMPROVE ADHESION OF PECVD CAP LAYERS IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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03/06/2001
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Application #:
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09121957
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Filing Dt:
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07/24/1998
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Title:
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CMOS WAVESHAPING BUFFER
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Patent #:
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Issue Dt:
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06/05/2001
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Application #:
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09135105
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Filing Dt:
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08/17/1998
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Title:
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METHODS AND APPARATUS FOR EXTRACTING PARASITIC CAPACITANCE VALUES FROM A PHYSICAL DESIGN OF AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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08/29/2000
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Application #:
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09136459
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Filing Dt:
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08/19/1998
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Title:
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SEMICONDUCTOR HAVING SELF-ALIGNED, BURIED ETCH STOP FOR TRENCH AND MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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05/29/2001
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Application #:
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09144963
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Filing Dt:
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09/01/1998
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Title:
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MOSFET STRUCTURE HAVING IMPROVED SOURCE/DRAIN JUNCTION PERFORMANCE
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Patent #:
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Issue Dt:
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01/08/2002
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Application #:
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09150119
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Filing Dt:
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09/09/1998
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Title:
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METHOD AND APPARATUS FOR GENERATING ONE TIME PADS SIMULTANEOUSLY IN SEPARATE ENCRYPTION/DECRYPTION SYSTEMS
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Patent #:
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Issue Dt:
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07/04/2000
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Application #:
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09151172
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Filing Dt:
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09/10/1998
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Title:
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MOLDED LEAD FRAME BALL GRID ARRAY
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Patent #:
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Issue Dt:
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01/16/2001
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Application #:
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09154050
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Filing Dt:
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09/16/1998
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Title:
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INTEGRATED CIRCUIT DEVICE INTERCONNECTION TECHNIQUES
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Patent #:
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Issue Dt:
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11/30/1999
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Application #:
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09157631
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Filing Dt:
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09/21/1998
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Title:
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FLIP CHIP CIRCUIT ARRANGEMENT WITH REDISTRIBUTION LAYER THAT MINIMIZES CROSSTALK
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Patent #:
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Issue Dt:
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12/19/2000
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Application #:
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09158759
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Filing Dt:
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09/23/1998
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Title:
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DIFFERENTIAL VOLTAGE DIGITAL-TO-ANALOG CONVERTER
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Patent #:
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Issue Dt:
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07/10/2001
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Application #:
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09159424
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Filing Dt:
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09/24/1998
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Title:
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POINT TO POINT OR RING CONNECTABLE BUS BRIDGE AND AN INTERFACE WITH METHOD FOR ENHANCING LINK PERFORMANCE IN A POINT TO POINT CONNECTABLE BUS BRIDGE SYSTEM USING THE FIBRE CHANNEL
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Patent #:
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Issue Dt:
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08/14/2001
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Application #:
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09163061
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Filing Dt:
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09/29/1998
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Title:
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MICROPROCESSOR-BASED SERIAL BUS INTERFACE ARRANGEMENT AND METHOD
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Patent #:
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Issue Dt:
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10/17/2000
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Application #:
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09164167
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Filing Dt:
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09/30/1998
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Title:
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METHOD OF MAKING PHOTO ALIGNMENT STRUCTURE
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Patent #:
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Issue Dt:
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12/19/2000
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Application #:
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09167655
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Filing Dt:
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10/05/1998
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Title:
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VIA ALIGNMENT, ETCH COMPLETION, AND CRITICAL DIMENSION MEASUREMENT METHOD AND STRUCTURE
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Patent #:
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Issue Dt:
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11/27/2001
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Application #:
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09177789
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Filing Dt:
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10/22/1998
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Title:
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SYSTEM AND METHOD TO TEST INTERNAL PCI AGENTS
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09185411
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Filing Dt:
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11/03/1998
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Title:
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INTERGRATED CIRCUITRY, INTERFACE CIRCUIT OF AN INTEGRATED CIRCUIT DEVICE AND CIRCUITRY
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Patent #:
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Issue Dt:
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06/21/2005
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Application #:
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09186546
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Filing Dt:
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11/05/1998
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Title:
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SECURE MEMORY MANAGEMENT UNIT WHICH USES MULTIPLE CRYPTOGRAPHIC ALGORITHMS
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Patent #:
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09/11/2001
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Application #:
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09187325
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Filing Dt:
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11/06/1998
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Title:
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OPTIMIZING THE PERFORMANCE OF ASYNCHRONOUS BUS BRIDGES WITH DYNAMIC TRANSACTIONS
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Patent #:
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Issue Dt:
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07/03/2001
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Application #:
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09193549
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Filing Dt:
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11/17/1998
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Title:
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METHODS OF MONITORING AND MAINTAINING CONCENTRATIONS OF SELECTED SPECIES IN SOLUTIONS DURING SEMICONDUCTOR PROCESSING
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Patent #:
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Issue Dt:
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04/04/2000
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09196481
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Filing Dt:
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11/19/1998
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Title:
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MOISTURE BARRIER GAP FILL STRUCTURE AND METHOD FOR MAKING THE SAME
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Patent #:
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04/10/2001
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Application #:
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09197377
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Filing Dt:
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11/20/1998
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Title:
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METHOD OF USING FILMS HAVING OPTIMIZED OPTICAL PROPERTIES FOR CHEMICAL MECHANICAL POLISHING ENDPOINT DETECTION
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Patent #:
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11/13/2001
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09201450
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11/30/1998
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Title:
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CONCURRENT SERIAL INTERCONNECT FOR INTEGRATING FUNCTIONAL BLOCKS IN AN INTEGRATED CIRCUIT DEVICE
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Patent #:
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03/19/2002
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09205807
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12/04/1998
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Title:
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MPEG-2 TRANSPORT DEMULTIPLEXOR ARCHITECTURE WITH NON-TIME-CRITICAL POST-PROCESSING OF PACKET INFORMATION
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01/23/2001
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09210103
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12/11/1998
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Title:
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SMART TARGET MECHANISM FOR ELIMINATING DUAL ADDRESS CYCLES IN A PERIPHERAL COMPONENT INTERCONNECT ENVIRONMENT
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Patent #:
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02/12/2002
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09212151
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12/15/1998
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Title:
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Patent #:
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08/29/2000
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09212854
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12/16/1998
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Title:
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METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION IN DIGITAL ELECTRONIC CIRCUITS
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08/15/2000
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09215071
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12/18/1998
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Title:
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REMOVAL OF INORGANIC ANTI-REFLECTIVE COATING USING FLUORINE ETCH PROCESS
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Patent #:
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03/05/2002
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09215516
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12/17/1998
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Title:
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METHOD OF AUTOMATICALLY GENERATING NEW TEST PROGRAMS FOR MIXED-SIGNAL INTEGRATED CIRCUIT BASED ON REUSABLE TEST-BLOCK TEMPLETES ACCORDING TO USER-PROVIDED DRIVER FILE
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Patent #:
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02/01/2000
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09215902
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12/18/1998
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Title:
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COMPOSITE METALLIZATION STRUCTURES FOR IMPROVED POST BONDING RELIABILITY
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02/12/2002
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09215942
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12/18/1998
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Title:
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METHOD AND ARRANGEMENT FOR RAPID SILICON PROTOTYPING
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Patent #:
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09/18/2001
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09216385
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12/18/1998
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Title:
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SIMULATION TOOL INPUT FILE GENERATOR FOR INTERFACE CIRCUITRY
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Patent #:
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12/26/2000
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09216701
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12/18/1998
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Title:
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Patent #:
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05/15/2001
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09227031
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01/07/1999
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Title:
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09/05/2000
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09227034
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01/07/1999
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Title:
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METHOD OF USING A POLISH STOP FILM TO CONTROL DISHING DURING COPPER CHEMICAL MECHANICAL POLISHING
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12/11/2001
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09227122
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01/08/1999
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Title:
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SYSTEM FOR MAXIMIZING DMA TRANSFERS OF ARBITRARILY ALIGNED DATA HAVING SCATTER BUFFER TO TRANSFER INFORMATION TO SCATTERED LOCATIONS IN MAIN MEMORY AND GATHER BUFFER TO GATHER THE SCATTERED INFORMATION
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10/03/2000
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09228707
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01/12/1999
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Title:
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MICRO-ELECTROMECHANICAL SYSTEM AND VOLTAGE SHIFTER, METHOD OF SYNCHRONIZING AN ELECTRONIC SYSTEM AND A NICROMECHANICAL SYSTEM OF A MICRO-ELECTROMECHANICAL SYSTEM
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12/26/2000
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09234235
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01/20/1999
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Title:
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METHODS FOR MAKING RELIABLE VIA STRUCTURES HAVING HYDROPHOBIC INNER WALL SURFACES
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11/21/2000
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09239458
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01/28/1999
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05/08/2001
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09239461
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01/28/1999
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Title:
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METHOD FOR ELIMINATING DUAL ADDRESS CYCLES IN A PERIPHERAL COMPONENT INTERCONNECT ENVIRONMENT
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02/13/2001
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09241175
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02/01/1999
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Title:
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POWER-ON-RESET LOGIC WITH SECURE POWER DOWN CAPABILITY
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07/10/2001
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09241263
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02/01/1999
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Title:
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METHOD AND APPARATUS FOR SECURE ADDRESS RE-MAPPING
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10/10/2000
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09241270
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02/01/1999
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ALTERNATIVE PLASMA CHEMISTRY FOR ENHANCED PHOTORESIST REMOVAL
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12/04/2001
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09248777
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02/12/1999
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Title:
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03/21/2000
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09249225
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02/11/1999
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OXIDE WIRE BOND INSULATION IN SEMICONDUCTOR ASSEMBLIES
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01/23/2001
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09249227
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02/11/1999
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SIO2 WIRE BOND INSULATION IN SEMICONDUCTOR ASSEMBLIES
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04/24/2001
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09255407
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02/22/1999
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SYSTEM AND METHOD TO PREDICT CONFIGURATION OF A BUS TARGET
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09/11/2001
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09262439
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03/04/1999
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08/27/2002
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09264205
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03/03/1999
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Title:
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SYSTEM FOR PRIMING A LATCH BETWEEN TWO MEMORIES AND TRANSFERRING DATA VIA THE LATCH IN SUCCESSIVE CLOCK CYCLE THEREAFTER
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