Total properties:
595
Page
6
of
6
Pages:
1 2 3 4 5 6 |
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2001
|
Application #:
|
09264742
|
Filing Dt:
|
03/08/1999
|
|
Title:
|
ARRANGEMENT AND METHOD FOR CALIBRATING OPTICAL LINE SHORTENING MEASUREMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2001
|
Application #:
|
09271737
|
Filing Dt:
|
03/18/1999
|
|
Title:
|
SEMICONDUCTOR DEVICE WITH TRANSPARENT LINK AREA FOR SILICIDE APPLICATIONS AND FABRICATION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2000
|
Application #:
|
09273077
|
Filing Dt:
|
03/19/1999
|
|
Title:
|
METHODS OF INSPECTING FOR MASK-DEFINED, FEATURE DIMENSIONAL CONFORMITY BETWEEN MULTIPLE MASKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2001
|
Application #:
|
09277860
|
Filing Dt:
|
03/26/1999
|
|
Title:
|
DIRECT MEMORY ACCESS SYSTEM AND METHOD TO BRIDGE PCI BUS PROTOCOLS AND HITACHI SH4 PROTOCOLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2000
|
Application #:
|
09282291
|
Filing Dt:
|
03/31/1999
|
|
Title:
|
METHOD OF PROTECTING AN INTEGRATED CIRCUIT, METHOD OF OPERATING INTEGRATED CIRCUITRY, AND METHOD OF OPERATING CASCODE CIRCUITRY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2001
|
Application #:
|
09283049
|
Filing Dt:
|
04/01/1999
|
|
Title:
|
CMP PAD CONDITIONER ARRANGEMENT AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2001
|
Application #:
|
09283171
|
Filing Dt:
|
04/01/1999
|
|
Title:
|
METHOD AND ARRANGEMENT FOR CONTROLLING MULTIPLY-ACTIVATED TEST ACCESS PORT CONTROL MODULES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2001
|
Application #:
|
09283648
|
Filing Dt:
|
04/01/1999
|
|
Title:
|
METHOD AND ARRANGEMENT FOR HIERARCHICAL CONTROL OF MULTIPLE TEST ACCESS PORT CONTROL MODULES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2002
|
Application #:
|
09283809
|
Filing Dt:
|
04/01/1999
|
|
Title:
|
METHOD AND ARRANGEMENT FOR CONTROLLING MULTIPLE TEST ACCESS PORT CONTROL MODULES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2001
|
Application #:
|
09290154
|
Filing Dt:
|
04/12/1999
|
|
Title:
|
HIGH PERFORMANCE FLIP-CHIP SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2001
|
Application #:
|
09291402
|
Filing Dt:
|
04/13/1999
|
|
Title:
|
METHOD AND SYSTEM FOR OPTIMIZED DATA TRANSFERS IN A MIXED 64-BIT/32-BIT PCI ENVIRONMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2001
|
Application #:
|
09291788
|
Filing Dt:
|
04/14/1999
|
|
Title:
|
PATTERNED POLISHING PAD FOR USE IN CHEMICAL MECHANICAL POLISHING OF SEMICONDUCTOR WAFERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2002
|
Application #:
|
09293077
|
Filing Dt:
|
04/16/1999
|
|
Title:
|
SYSTEM AND METHOD TO OPTIMIZE READ PERFORMANCE WHILE ACCEPTING WRITE DATA IN A PCI BUS ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2002
|
Application #:
|
09299707
|
Filing Dt:
|
04/26/1999
|
|
Title:
|
SYSTEM FOR CROSS STREAM REGASSIFIER FOR IMPROVED CHEMICAL MECHANICAL POLISHING IN THE MANUFACTURE OF SEMICONDUCTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2001
|
Application #:
|
09301186
|
Filing Dt:
|
04/28/1999
|
|
Title:
|
PROGRAMMABLE FUSE AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2001
|
Application #:
|
09303830
|
Filing Dt:
|
05/03/1999
|
|
Title:
|
METHOD OF MAKING SHALLOW JUNCTION SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2002
|
Application #:
|
09303891
|
Filing Dt:
|
05/03/1999
|
|
Title:
|
METHOD AND APPARATUS FOR REDUCING INTERCONNECT RESISTANCE USING AN INTERCONNECT WELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2001
|
Application #:
|
09303998
|
Filing Dt:
|
05/03/1999
|
|
Title:
|
REDUCING THE FORMATION OF ELECTRICAL LEAKAGE PATHWAYS DURING MANUFACTURE OF AN ELECTRONIC DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2001
|
Application #:
|
09304886
|
Filing Dt:
|
05/04/1999
|
|
Title:
|
APPARATUS FOR AUTOMATED PILLAR LAYOUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2002
|
Application #:
|
09305977
|
Filing Dt:
|
05/05/1999
|
|
Title:
|
METHOD AND APPARATUS FOR A GASEOUS ENVIRONMENT PROVIDING IMPROVED CONTROL OF CMP PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2000
|
Application #:
|
09306239
|
Filing Dt:
|
05/06/1999
|
|
Title:
|
MOISTURE REPELLANT INTEGRATED CIRCUIT DIELECTRIC MATERIAL COMBINATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2001
|
Application #:
|
09306517
|
Filing Dt:
|
05/06/1999
|
|
Title:
|
PACKAGE STRUCTURE FOR LOW COST AND ULTRA THIN CHIP SCALE PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2001
|
Application #:
|
09310470
|
Filing Dt:
|
05/12/1999
|
|
Title:
|
METHOD FOR DETERMINING NITROGEN CONCENTRATION IN A FILM OF NITRIDED OXIDE MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2001
|
Application #:
|
09312730
|
Filing Dt:
|
05/14/1999
|
|
Title:
|
METHOD FOR ENDPOINT DETECTION DURING DRY ETCH OF SUBMICRON FEATURES IN A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2001
|
Application #:
|
09312776
|
Filing Dt:
|
05/17/1999
|
|
Title:
|
IN-SITU BACKGRIND WAFER THICKNESS MONITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2001
|
Application #:
|
09313685
|
Filing Dt:
|
05/18/1999
|
|
Title:
|
INTERCONNECT LAYOUT PATTERN FOR INTEGRATED CIRCUIT PACKAGES AND THE LIKE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2002
|
Application #:
|
09313933
|
Filing Dt:
|
05/18/1999
|
|
Title:
|
SYSTEM AND METHOD TO REDUCE POWER CONSUMPTION IN ADVANCED RISC MACHINE (ARM) BASED SYSTEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2002
|
Application #:
|
09315596
|
Filing Dt:
|
05/20/1999
|
|
Title:
|
SEMICONDUCTOR BLOCKING LAYER FOR PREVENTING UV RADIATION DAMAGE TO MOS GATE OXIDES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2003
|
Application #:
|
09321699
|
Filing Dt:
|
05/28/1999
|
|
Title:
|
METHOD AND DEVICE FOR FRAME RATE DETERMINATION USING CORRELATION METRICS AND FRAME QUALITY INDICATORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2001
|
Application #:
|
09322172
|
Filing Dt:
|
05/28/1999
|
|
Title:
|
METHOD AND APPARATUS FOR PROVIDING AN EMBEDDED FLASH-EEPROM TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2005
|
Application #:
|
09322259
|
Filing Dt:
|
05/28/1999
|
|
Title:
|
REDUCING ARTIFACT GENERATION IN A VOCODER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2003
|
Application #:
|
09322703
|
Filing Dt:
|
05/28/1999
|
|
Title:
|
EFFICIENT APPARATUS AND METHOD FOR GENERATING A TRELLIS CODE FROM A SHARED STATE COUNTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2001
|
Application #:
|
09330241
|
Filing Dt:
|
06/10/1999
|
|
Title:
|
METHODS OF PACKAGING AN INTEGRATED CIRCUIT AND METHODS OF FORMING AN INTEGRATED CIRCUIT PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2001
|
Application #:
|
09336270
|
Filing Dt:
|
06/18/1999
|
|
Title:
|
CUSTOM LASER CONDUCTOR LINKAGE FOR INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09337089
|
Filing Dt:
|
06/21/1999
|
|
Title:
|
SET-ASSOCIATIVE CACHE-MANAGEMENT METHOD WITH PARALLEL AND SINGLE-SET SEQUENTIAL READS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2001
|
Application #:
|
09337151
|
Filing Dt:
|
06/21/1999
|
|
Title:
|
SEMICONDUCTOR ARRANGEMENT HAVING CAPACITIVE STRUCTURE AND MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2001
|
Application #:
|
09340487
|
Filing Dt:
|
06/30/1999
|
|
Title:
|
LASER INTERFEROMETRY ENDPOINT DETECTION WITH WINDOWLESS POLISHING PAD FOR CHEMICAL MECHANICAL POLISHING PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2001
|
Application #:
|
09348793
|
Filing Dt:
|
07/07/1999
|
|
Title:
|
SEMICONDUCTOR DEVICE ARRANGEMENT HAVING CONFIGURATION VIA ADJACENT BOND PAD CODING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2001
|
Application #:
|
09353306
|
Filing Dt:
|
07/13/1999
|
|
Title:
|
DESIGN FOR TEST AREA OPTIMIZATION ALGORITHM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09360783
|
Filing Dt:
|
07/26/1999
|
|
Title:
|
A SEMICONDUCTOR WAFER, A CHEMICAL-MECHANICAL ALIGNMENT MARK, AND AN APPARATUS FOR IMPROVING ALIGNMENT FOR METAL MASKING IN CONJUNCTION WITH OXIDE AND TUNGSTEN CMP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2002
|
Application #:
|
09366504
|
Filing Dt:
|
08/03/1999
|
|
Title:
|
ARITHMETIC UNIT, DIGITAL SIGNAL PROCESSOR, METHOD OF SCHEDULING MULTIPLICATION IN AN ARITHMETIC UNIT, METHOD OF SELECTIVELY DELAYING ADDING AND METHOD OF SELECTIVELY ADDING DURING A FIRST OR SECOND CLOCK CYCLE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2001
|
Application #:
|
09368400
|
Filing Dt:
|
08/04/1999
|
|
Title:
|
COMPARATORS AND COMPARISON METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09377043
|
Filing Dt:
|
08/18/1999
|
|
Title:
|
MANUFACTURE OF AN INTEGRATED CIRCUIT ISOLATION STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2000
|
Application #:
|
09387868
|
Filing Dt:
|
09/01/1999
|
|
Title:
|
SINGLE ADDRESS QUEUE FOR HANDLING MULTIPLE PRIORITY REQUESTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2001
|
Application #:
|
09390455
|
Filing Dt:
|
09/07/1999
|
|
Title:
|
ULTRASONIC TRANSDUCER SLURRY DISPENSER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2002
|
Application #:
|
09394395
|
Filing Dt:
|
09/13/1999
|
|
Title:
|
INTERFACE AND PROCESS FOR HANDLING OUT-OF-ORDER DATA TRANSACTIONS AND SYNCHRONIZING EVENTS IN A SPLIT-BUS SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2002
|
Application #:
|
09394866
|
Filing Dt:
|
09/13/1999
|
|
Title:
|
SELF-ALIGNED ETCH-STOP LAYER FORMATION FOR SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2001
|
Application #:
|
09396104
|
Filing Dt:
|
09/14/1999
|
|
Title:
|
SEMICONDUCTOR STRUCTURES FOR SUPPRESSING GATE OXIDE PLASMA CHARGING DAMAGE AND METHODS FOR MAKING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2001
|
Application #:
|
09400738
|
Filing Dt:
|
09/21/1999
|
|
Title:
|
METHOD AND SYSTEM FOR ACCURATE TEMPORAL DETERMINATION OF REAL-TIME EVENTS WITHIN A UNIVERSAL SERIAL BUS SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2002
|
Application #:
|
09401046
|
Filing Dt:
|
09/22/1999
|
|
Title:
|
METHOD AND SYSTEM FOR CACHE REPLACEMENT AMONG CONFIGURABLE CACHE SETS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2000
|
Application #:
|
09405353
|
Filing Dt:
|
09/24/1999
|
|
Title:
|
DIFFERENTIAL DEVICES AND DIFFERENTIAL TRANSCEIVER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2003
|
Application #:
|
09405377
|
Filing Dt:
|
09/24/1999
|
|
Title:
|
METHOD AND APPARATUS FOR TIME TRACKING A SIGNAL USING HARDWARE AND SOFTWARE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2002
|
Application #:
|
09410186
|
Filing Dt:
|
09/30/1999
|
|
Title:
|
FLUID DISPENSING FIXED ABRASIVE POLISHING PAD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2003
|
Application #:
|
09410942
|
Filing Dt:
|
10/04/1999
|
|
Title:
|
DIE PAD CRACK ABSORPTION SYSTEM AND METHOD FOR INTEGRATED CIRCUIT CHIP FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2000
|
Application #:
|
09417417
|
Filing Dt:
|
10/13/1999
|
|
Title:
|
METHOD AND SYSTEM FOR IN-SITU OPTIMIZATION FOR SEMICONDUCTOR WAFERS IN A CHEMICAL MECHANICAL POLISHING PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2001
|
Application #:
|
09418272
|
Filing Dt:
|
10/14/1999
|
|
Title:
|
MASTER/SLAVE MULTI-PROCESSOR ARRANGEMENT AND METHOD THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2001
|
Application #:
|
09428733
|
Filing Dt:
|
10/28/1999
|
|
Title:
|
METHOD FOR SUPPRESSING NARROW WIDTH EFFECTS IN CMOS TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2003
|
Application #:
|
09429540
|
Filing Dt:
|
10/28/1999
|
|
Title:
|
METHODS FOR FORMING CO-AXIAL INTERCONNECT LINES IN A CMOS PROCESS FOR HIGH SPEED APPLICATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2000
|
Application #:
|
09430420
|
Filing Dt:
|
10/29/1999
|
|
Title:
|
ON-CHIP DECOUPLING CAPACITOR SYSTEM WITH PARALLEL FUSE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2001
|
Application #:
|
09431841
|
Filing Dt:
|
11/02/1999
|
|
Title:
|
METHOD OF FORMING DUAL GATE OXIDE LAYERS OF VARYING THICKNESS ON A SINGLE SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
09432666
|
Filing Dt:
|
11/02/1999
|
|
Title:
|
USE OF AN INSULATING SPACER TO PREVENT THRESHOLD VOLTAGE ROLL-OFF IN NARROW DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2001
|
Application #:
|
09434218
|
Filing Dt:
|
11/04/1999
|
|
Title:
|
NON-POWER-OF-TWO GRAY-CODE COUNTER AND BINARY INCREMENTER THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2002
|
Application #:
|
09434636
|
Filing Dt:
|
11/04/1999
|
|
Title:
|
INTEGRATED CIRCUIT (IC) PLATING DEPOSITION SYSTEM AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2001
|
Application #:
|
09435894
|
Filing Dt:
|
11/08/1999
|
|
Title:
|
CIRCUITS, BARREL SHIFTERS, AND METHODS OF MANIPULATING A BIT PATTERN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2001
|
Application #:
|
09436937
|
Filing Dt:
|
11/08/1999
|
|
Title:
|
METHOD OF USING A POLISH STOP FILM TO CONTROL DISHING DURING COPPER CHEMICAL MECHANICAL POLISHING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2001
|
Application #:
|
09439021
|
Filing Dt:
|
11/12/1999
|
|
Title:
|
PROCESS TO IMPROVE ADHESION OF CAP LAYERS IN INTERGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2001
|
Application #:
|
09439098
|
Filing Dt:
|
11/12/1999
|
|
Title:
|
AIR GAP DIELECTRIC IN SELF-ALIGNED VIA STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
09439564
|
Filing Dt:
|
11/12/1999
|
|
Title:
|
FLEXIBLE PIN COUNT PACKAGE FOR SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2005
|
Application #:
|
09443883
|
Filing Dt:
|
11/18/1999
|
|
Title:
|
METHOD OF DISCRIMINATING BETWEEN DIFFERENT TYPES OF SCAN FAILURES, COMPUTER READABLE CODE TO CAUSE A DISPLAY TO GRAPHICALLY DEPICT ONE OR MORE SIMULATED SCAN OUTPUT DATA SETS VERSUS TIME AND A COMPUTER IMPLEMENTED CIRCUIT SIMULATION AND FAULT DETECTION SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2001
|
Application #:
|
09452291
|
Filing Dt:
|
11/30/1999
|
|
Title:
|
INCORPORATION OF NITROGEN-BASED GAS IN POLYSILICON GATE RE-OXIDATION TO IMPROVE HOT CARRIERPERFORMANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2002
|
Application #:
|
09461702
|
Filing Dt:
|
12/14/1999
|
|
Title:
|
WAVEGUIDE STRUCTURES INTEGRATED WITH STANDARD CMOS CIRCUITRY AND METHODS FOR MAKING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2001
|
Application #:
|
09466988
|
Filing Dt:
|
12/10/1999
|
|
Title:
|
INTELLIGENT GATE-LEVEL FILL METHODS FOR REDUCING GLOBAL PATTERN DENSITY EFFECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2001
|
Application #:
|
09467734
|
Filing Dt:
|
12/20/1999
|
|
Title:
|
THIN CAPACITIVE STRUCTURES AND METHODS FOR MAKING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2002
|
Application #:
|
09470296
|
Filing Dt:
|
12/22/1999
|
|
Title:
|
APPARATUS FOR PERFORMING CHEMICAL-MECHANICAL PLANARIZATION WITH IMPROVED PROCESS WINDOW, PROCESS FLEXIBILITY AND COST
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2002
|
Application #:
|
09470779
|
Filing Dt:
|
12/23/1999
|
|
Title:
|
METHODS FOR CONVERTING FEATURES TO A UNIFORM MICRON TECHNOLOGY IN AN INTEGRATED CIRCUIT DESIGN AND APPARATUS FOR DOING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2001
|
Application #:
|
09475698
|
Filing Dt:
|
12/30/1999
|
|
Title:
|
BACKEND PROCESS FOR FUSE LINK OPENING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2002
|
Application #:
|
09475889
|
Filing Dt:
|
12/30/1999
|
|
Title:
|
REDUCTION OF POWER CONSUMPTION WITH INCREASED STANDBY TIME IN WIRELESS COMMUNICATIONS DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2002
|
Application #:
|
09513009
|
Filing Dt:
|
02/25/2000
|
|
Title:
|
METHOD AND ARRANGEMENT FOR PASSING DATA BETWEEN A REFERENCE CHIP AND AN EXTERNAL BUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2001
|
Application #:
|
09519940
|
Filing Dt:
|
03/07/2000
|
|
Title:
|
Memory devices and memory reading methods
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2001
|
Application #:
|
09531103
|
Filing Dt:
|
03/17/2000
|
|
Title:
|
Scan testable circuit arrangement
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2002
|
Application #:
|
09593322
|
Filing Dt:
|
06/13/2000
|
|
Title:
|
SEMICONDUCTOR DEVICE WITH MISALIGNED VIA HOLE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2003
|
Application #:
|
09753824
|
Filing Dt:
|
01/02/2001
|
|
Title:
|
VOICE RECORDING AND PLAYBACK MODE USING THE G.726 HALF-RATE WITHIN THE PERSONAL HANDY PHONE SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2002
|
Application #:
|
09783689
|
Filing Dt:
|
02/14/2001
|
|
Publication #:
|
|
Pub Dt:
|
08/16/2001
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE WITH HIGH-TEMPERATURE-STABLE GATE ELECTRODE FOR SUB-MICRON APPLICATIONS AND FABRICATION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2003
|
Application #:
|
09795680
|
Filing Dt:
|
02/27/2001
|
|
Title:
|
SEMICONDUCTOR BLOCKING LAYER FOR PREVENTING UV RADIATION DAMAGE TO MOS GATE OXIDES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2002
|
Application #:
|
09797644
|
Filing Dt:
|
03/01/2001
|
|
Publication #:
|
|
Pub Dt:
|
07/12/2001
| | | | |
|
Title:
|
Set-associative cache-management method with parallel and single-set sequential reads
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2002
|
Application #:
|
09836936
|
Filing Dt:
|
04/17/2001
|
|
Publication #:
|
|
Pub Dt:
|
10/18/2001
| | | | |
|
Title:
|
METHOD OF MAKING A MOSFET STRUCTURE HAVING IMPROVED SOURCE/DRAIN JUNCTION PERFORMANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2002
|
Application #:
|
09850607
|
Filing Dt:
|
05/07/2001
|
|
Publication #:
|
|
Pub Dt:
|
09/13/2001
| | | | |
|
Title:
|
SEMICONDUCTOR ARRANGEMENT HAVING CAPACITIVE STRUCTURE AND MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2002
|
Application #:
|
09864615
|
Filing Dt:
|
05/23/2001
|
|
Publication #:
|
|
Pub Dt:
|
10/11/2001
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR PROVIDING AN EMBEDDED FLASH-EEPROM TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2002
|
Application #:
|
09874607
|
Filing Dt:
|
06/05/2001
|
|
Publication #:
|
|
Pub Dt:
|
10/04/2001
| | | | |
|
Title:
|
METHOD OF ILLUMINATION UNIFORMITY IN PHOTOLITHOGRAPHIC SYSTEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2002
|
Application #:
|
09912194
|
Filing Dt:
|
07/24/2001
|
|
Publication #:
|
|
Pub Dt:
|
11/15/2001
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE WITH TRANSPARENT LINK AREA FOR SILICIDE APPLICATIONS AND FABRICATION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2004
|
Application #:
|
09947430
|
Filing Dt:
|
09/05/2001
|
|
Publication #:
|
|
Pub Dt:
|
02/14/2002
| | | | |
|
Title:
|
HIGH PERFORMANCE CHIP/PACKAGE INDUCTOR INTEGRATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2003
|
Application #:
|
10003130
|
Filing Dt:
|
11/01/2001
|
|
Publication #:
|
|
Pub Dt:
|
04/25/2002
| | | | |
|
Title:
|
SEMICONDUCTOR PROCESSING METHODS AND STRUCTURES FOR DETERMINING ALIGNMENT DURING SEMICONDUCTOR WAFER PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2003
|
Application #:
|
10016930
|
Filing Dt:
|
12/13/2001
|
|
Title:
|
SMART RETRY SYSTEM THAT REDUCES WASTED BUS TRANSACTIONS ASSOCIATED WITH MASTER RETRIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2006
|
Application #:
|
10358979
|
Filing Dt:
|
02/05/2003
|
|
Publication #:
|
|
Pub Dt:
|
09/25/2003
| | | | |
|
Title:
|
DERATING FACTOR DETERMINATION FOR INTEGRATED CIRCUIT LOGIC DESIGN TOOLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2005
|
Application #:
|
10666484
|
Filing Dt:
|
09/19/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/25/2004
| | | | |
|
Title:
|
METHOD OF USING FILMS HAVING OPTIMIZED OPTICAL PROPERTIES FOR CHEMICAL MECHANICAL POLISHING ENDPOINT DETECTION
|
|
