Patent Assignment Details
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| Reel/Frame: | 018771/0472 | |
| Pages: | 4 |
| | Recorded: | 01/05/2007 | | |
| Attorney Dkt #: | 1026905-000032 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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11/30/2010
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Application #:
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11486107
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Filing Dt:
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07/14/2006
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Publication #:
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Pub Dt:
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05/31/2007
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Title:
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METHOD FOR DESIGNING A SEMICONDUCTOR INTEGRATED CIRCUIT LAYOUT CAPABLE OF REDUCING THE PROCESSING TIME FOR OPTICAL PROXIMITY EFFECT CORRECTION
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Assignees
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| 4-1. MARUNOUCHI 2-CHOME, CHIYODA-KU |
| TOKYO, JAPAN 100-6334 |
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| 1006, OAZA KADOMA |
| KADOMA-SHI, OSAKA, JAPAN 571-8501 |
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| 1758 SHIMONUMABE, NAKAHARA-KU |
| KAWASAKI, KANAGAWA, JAPAN 211-8668 |
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| 1-1, KAMIKODANAKA 4-CHOME, NAKAHARA-KU |
| KAWASAKI-SHI, KANAGAWA, JAPAN 211-8588 |
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| 1-1, SHIBAURA 1-CHOME, MINATO-KU |
| TOKYO, JAPAN 105-0023 |
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Correspondence name and address
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BUCHANAN INGERSOLL & ROONEY PC
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P.O. BOX 1404
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ALEXANDRIA, VA 22313-1404
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