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Patent Assignment Details
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Reel/Frame:018787/0325   Pages: 3
Recorded: 01/19/2007
Attorney Dkt #:013176.0100
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 10
1
Patent #:
Issue Dt:
06/13/1995
Application #:
07981133
Filing Dt:
11/24/1992
Title:
PROCESS FOR FABRICATING MATERIALS FOR FERROELECTRIC, HIGH DIELECTRIC CONSTANT, AND INTEGRATED CIRCUIT APPLICATIONS
2
Patent #:
Issue Dt:
07/18/1995
Application #:
08065656
Filing Dt:
05/21/1993
Title:
PROCESS FOR FABRICATING LAYERED SUPERLATTICE MATERIALS AND MAKING ELECTRONIC DEVICES INCLUDING SAME
3
Patent #:
Issue Dt:
07/15/1997
Application #:
08090767
Filing Dt:
07/12/1993
Title:
CHEMICAL VAPOR DEPOSITION PROCESS FOR FABRICATING LAYERED SUPERLATTICE MATERIALS
4
Patent #:
Issue Dt:
11/28/1995
Application #:
08308647
Filing Dt:
09/19/1994
Title:
FERROELECTRIC CAPACITIVE ELEMENT
5
Patent #:
Issue Dt:
01/02/1996
Application #:
08319809
Filing Dt:
10/07/1994
Title:
FERROELECTRIC MEMORY
6
Patent #:
Issue Dt:
07/30/1996
Application #:
08330989
Filing Dt:
10/28/1994
Title:
FERROELECTRIC MEMORY AND NON-VOLATILE MEMEORY CELL FOR SAME
7
Patent #:
Issue Dt:
11/14/1995
Application #:
08383575
Filing Dt:
02/03/1995
Title:
PROCESS FOR FABRICATING FERROELECTRIC INTEGRATED CIRCUIT
8
Patent #:
Issue Dt:
04/16/1996
Application #:
08395582
Filing Dt:
02/27/1995
Title:
METHOD AND APPARATUS FOR REDUCED FATIGUE IN FERROELECTRIC MEMORY ELEMENTS
9
Patent #:
Issue Dt:
06/06/2000
Application #:
08405953
Filing Dt:
03/17/1995
Title:
PROCESS FOR FABRICATING LAYERED SUPERLATTICE MATERIALS AND MAKING ELECTRONIC DEVICES INCLUDING SAME
10
Patent #:
Issue Dt:
04/16/1996
Application #:
08407760
Filing Dt:
03/21/1995
Title:
LOW TEMPERATURE PROCESS FOR FABRICATING LAYERED SUPERLATTICE MATERIALSAND MAKING ELECTRONIC DEVICES INCLUDING SAME
Assignor
1
Exec Dt:
12/08/2006
Assignee
1
5055 MARK DABLING BOULEVARD
COLORADO SPRINGS, COLORADO 80918
Correspondence name and address
CARL A. FOREST
PATTON BOGGS LLP
1660 LINCOLN STREET, SUITE 1900
DENVER, CO 80264

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