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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	018891/0599			Pages:	28
		Recorded:	02/09/2007
Attorney Dkt #:	22144-001001
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 50

Patent #:	6606684	Issue Dt:	08/12/2003	Application #:	09541114	Filing Dt:	03/31/2000
Title:	MULTI-TIERED MEMORY BANK HAVING DIFFERENT DATA BUFFER SIZES WITH A PROGRAMMABLE BANK SELECT

Patent #:	6725360	Issue Dt:	04/20/2004	Application #:	09541116	Filing Dt:	03/31/2000
Title:	SELECTIVELY PROCESSING DIFFERENT SIZE DATA IN MULTIPLIER AND ALU PATHS IN PARALLEL

Patent #:	6446181	Issue Dt:	09/03/2002	Application #:	09541117	Filing Dt:	03/31/2000
Title:	SYSTEM HAVING A CONFIGURABLE CACHE/SRAM MEMORY

Patent #:	6601077	Issue Dt:	07/29/2003	Application #:	09541148	Filing Dt:	03/31/2000
Title:	DSP UNIT FOR MULTI-LEVEL GLOBAL ACCUMULATION

Patent #:	6700996	Issue Dt:	03/02/2004	Application #:	09589624	Filing Dt:	06/07/2000
Title:	ADAPTIVE EARLY EXIT TECHNIQUES IN IMAGE CORRELATION

Patent #:	6654502	Issue Dt:	11/25/2003	Application #:	09589630	Filing Dt:	06/07/2000
Title:	ADAPTIVE EARLY EXIT TECHNIQUES IN IMAGE CORRELATION

Patent #:	6907080	Issue Dt:	06/14/2005	Application #:	09590028	Filing Dt:	06/07/2000
Title:	ADAPTIVE EARLY EXIT TECHNIQUES IN IMAGE CORRELATION

Patent #:	7120781	Issue Dt:	10/10/2006	Application #:	09608983	Filing Dt:	06/30/2000
Title:	GENERAL PURPOSE REGISTER FILE ARCHITECTURE FOR ALIGNED SIMD

Patent #:	6760800	Issue Dt:	07/06/2004	Application #:	09672289	Filing Dt:	09/28/2000
Title:	EVENT VECTOR TABLE OVERRIDE

Patent #:	6948056	Issue Dt:	09/20/2005	Application #:	09675066	Filing Dt:	09/28/2000
Title:	MAINTAINING EVEN AND ODD ARRAY POINTERS TO EXTREME VALUES BY SEARCHING AND COMPARING MULTIPLE ELEMENTS CONCURRENTLY WHERE A POINTER IS ADJUSTED AFTER PROCESSING TO ACCOUNT FOR A NUMBER OF PIPELINE STAGES

Patent #:	7155570	Issue Dt:	12/26/2006	Application #:	09675569	Filing Dt:	09/29/2000
Title:	FIFO WRITE/LIFO READ TRACE BUFFER WITH SOFTWARE AND HARDWARE LOOP COMPRESSION

Patent #:	6754808	Issue Dt:	06/22/2004	Application #:	09675712	Filing Dt:	09/29/2000
Title:	VALID BIT GENERATION AND TRACKING IN A PIPELINED PROCESSOR

Patent #:	7069420	Issue Dt:	06/27/2006	Application #:	09675815	Filing Dt:	09/28/2000
Title:	DECODE AND DISPATCH OF MULTI-ISSUE AND MULTIPLE WIDTH INSTRUCTIONS

Patent #:	6976151	Issue Dt:	12/13/2005	Application #:	09675816	Filing Dt:	09/28/2000
Title:	DECODING AN INSTRUCTION PORTION AND FORWARDING PART OF THE PORTION TO A FIRST DESTINATION, RE-ENCODING A DIFFERENT PART OF THE PORTION AND FORWARDING TO A SECOND DESTINATION

Patent #:	7082516	Issue Dt:	07/25/2006	Application #:	09675817	Filing Dt:	09/28/2000
Title:	ALIGNING INSTRUCTIONS USING A VARIABLE WIDTH ALIGNMENT ENGINE HAVING AN INTELLIGENT BUFFER REFILL MECHANISM

Patent #:	6789184	Issue Dt:	09/07/2004	Application #:	09676058	Filing Dt:	09/29/2000
Title:	INSTRUCTION ADDRESS GENERATION AND TRACKING IN A PIPELINED PROCESSOR

Patent #:	6728870	Issue Dt:	04/27/2004	Application #:	09680894	Filing Dt:	10/06/2000
Title:	REGISTER MOVE OPERATIONS

Patent #:	6665795	Issue Dt:	12/16/2003	Application #:	09684113	Filing Dt:	10/06/2000
Title:	RESETTING A PROGRAMMABLE PROCESSOR

Patent #:	7366876	Issue Dt:	04/29/2008	Application #:	09704467	Filing Dt:	10/31/2000
Title:	EFFICIENT EMULATION INSTRUCTION DISPATCH BASED ON INSTRUCTION WIDTH

Patent #:	6766444	Issue Dt:	07/20/2004	Application #:	09705070	Filing Dt:	11/02/2000
Title:	HARDWARE LOOPS

Patent #:	6898693	Issue Dt:	05/24/2005	Application #:	09705088	Filing Dt:	11/02/2000
Title:	HARDWARE LOOPS

Patent #:	6842812	Issue Dt:	01/11/2005	Application #:	09705207	Filing Dt:	11/02/2000
Title:	EVENT HANDLING

Patent #:	6748523	Issue Dt:	06/08/2004	Application #:	09705217	Filing Dt:	11/02/2000
Title:	HARDWARE LOOPS

Patent #:	7028165	Issue Dt:	04/11/2006	Application #:	09731198	Filing Dt:	12/06/2000
Publication #:	US20020069348	Pub Dt:	06/06/2002
Title:	PROCESSOR STALLING USING A SET OF STALL SIGNALS THAT ARE SPECIFIC TO STAGES OF A PIPELINE

Patent #:	7472259	Issue Dt:	12/30/2008	Application #:	09731523	Filing Dt:	12/06/2000
Publication #:	US20020103991	Pub Dt:	08/01/2002
Title:	MULTI-CYCLE INSTRUCTIONS

Patent #:	6823448	Issue Dt:	11/23/2004	Application #:	09738081	Filing Dt:	12/15/2000
Publication #:	US20020078334	Pub Dt:	06/20/2002
Title:	EXCEPTION HANDLING USING AN EXCEPTION PIPELINE IN A PIPELINED PROCESSOR

Patent #:	6789187	Issue Dt:	09/07/2004	Application #:	09738082	Filing Dt:	12/15/2000
Publication #:	US20020078336	Pub Dt:	06/20/2002
Title:	RESETTING PROCESSOR BY PROVIDEING A EXTENDED RESET SIGNAL TO DISABLE INSTRUCTION REQUEST LOGIC AND SUSPEND INSTRUCTION FETCHES

Patent #:	7168032	Issue Dt:	01/23/2007	Application #:	09738405	Filing Dt:	12/15/2000
Publication #:	US20020078420	Pub Dt:	06/20/2002
Title:	DATA SYNCHRONIZATION FOR A TEST ACCESS PORT

Patent #:	6986026	Issue Dt:	01/10/2006	Application #:	09738649	Filing Dt:	12/15/2000
Publication #:	US20040073780	Pub Dt:	04/15/2004
Title:	SINGLE-STEP PROCESSING AND SELECTING DEBUGGING MODES

Patent #:	6829701	Issue Dt:	12/07/2004	Application #:	09739092	Filing Dt:	12/15/2000
Publication #:	US20020078329	Pub Dt:	06/20/2002
Title:	WATCHPOINT ENGINE FOR A PIPELINED PROCESSOR

Patent #:	6920547	Issue Dt:	07/19/2005	Application #:	09742745	Filing Dt:	12/20/2000
Publication #:	US20020078326	Pub Dt:	06/20/2002
Title:	REGISTER ADJUSTMENT BASED ON ADJUSTMENT VALUES DETERMINED AT MULTIPLE STAGES WITHIN A PIPELINE OF A PROCESSOR

Patent #:	7065636	Issue Dt:	06/20/2006	Application #:	09745104	Filing Dt:	12/20/2000
Publication #:	US20020078333	Pub Dt:	06/20/2002
Title:	HARDWARE LOOPS AND PIPELINE SYSTEM USING ADVANCED GENERATION OF LOOP PARAMETERS

Patent #:	6760830	Issue Dt:	07/06/2004	Application #:	09751507	Filing Dt:	12/29/2000
Publication #:	US20020124039	Pub Dt:	09/05/2002
Title:	MODULO ADDRESSING

Patent #:	6763453	Issue Dt:	07/13/2004	Application #:	09753081	Filing Dt:	12/28/2000
Publication #:	US20020087853	Pub Dt:	07/04/2002
Title:	SECURITY ON HARDWARE LOOPS

Patent #:	6898695	Issue Dt:	05/24/2005	Application #:	09820514	Filing Dt:	03/28/2001
Publication #:	US20020144089	Pub Dt:	10/03/2002
Title:	USE OF A FUTURE FILE FOR DATA ADDRESS CALCULATIONS IN A PIPELINED PROCESSOR

Patent #:	6889316	Issue Dt:	05/03/2005	Application #:	09820570	Filing Dt:	03/28/2001
Publication #:	US20020144093	Pub Dt:	10/03/2002
Title:	METHOD AND APPARATUS FOR RESTORING REGISTERS AFTER CANCELLING A MULTI-CYCLE INSTRUCTION

Patent #:	6920515	Issue Dt:	07/19/2005	Application #:	09823095	Filing Dt:	03/29/2001
Publication #:	US20020144041	Pub Dt:	10/03/2002
Title:	EARLY EXCEPTION DETECTION

Patent #:	7124285	Issue Dt:	10/17/2006	Application #:	09823276	Filing Dt:	03/29/2001
Publication #:	US20020144100	Pub Dt:	10/03/2002
Title:	PEAK POWER REDUCTION WHEN UPDATING FUTURE FILE

Patent #:	7043582	Issue Dt:	05/09/2006	Application #:	10236856	Filing Dt:	09/06/2002
Publication #:	US20040049621	Pub Dt:	03/11/2004
Title:	SELF-NESTING INTERRUPTS

Patent #:	7313739	Issue Dt:	12/25/2007	Application #:	10335149	Filing Dt:	12/31/2002
Publication #:	US20040128596	Pub Dt:	07/01/2004
Title:	METHOD AND APPARATUS FOR TESTING EMBEDDED CORES

Patent #:	6820102	Issue Dt:	11/16/2004	Application #:	10630517	Filing Dt:	07/29/2003
Publication #:	US20040071041	Pub Dt:	04/15/2004
Title:	DSP UNIT FOR MULTI-LEVEL GLOBAL ACCUMULATION

Patent #:	6898690	Issue Dt:	05/24/2005	Application #:	10639020	Filing Dt:	08/11/2003
Publication #:	US20040034739	Pub Dt:	02/19/2004
Title:	MULTI-TIERED MEMORY BANK HAVING DIFFERENT DATA BUFFER SIZES WITH A PROGRAMMABLE BANK SELECT

Patent #:	7154950	Issue Dt:	12/26/2006	Application #:	10721593	Filing Dt:	11/24/2003
Publication #:	US20040105496	Pub Dt:	06/03/2004
Title:	ADAPTIVE EARLY EXIT TECHNIQUES IN IMAGE CORRELATION

Patent #:	7031498	Issue Dt:	04/18/2006	Application #:	10775261	Filing Dt:	02/09/2004
Publication #:	US20040156532	Pub Dt:	08/12/2004
Title:	ADAPTIVE EARLY EXIT TECHNIQUES IN IMAGE CORRELATION

Patent #:	7047271	Issue Dt:	05/16/2006	Application #:	10828913	Filing Dt:	04/20/2004
Publication #:	US20040199558	Pub Dt:	10/07/2004
Title:	DSP EXECUTION UNIT FOR EFFICIENT ALTERNATE MODES FOR PROCESSING MULTIPLE DATA SIZES

Patent #:	7036000	Issue Dt:	04/25/2006	Application #:	10847837	Filing Dt:	05/17/2004
Publication #:	US20040210744	Pub Dt:	10/21/2004
Title:	VALID BIT GENERATION AND TRACKING IN A PIPELINED PROCESSOR

Patent #:	7272705	Issue Dt:	09/18/2007	Application #:	11135862	Filing Dt:	05/23/2005
Publication #:	US20050223205	Pub Dt:	10/06/2005
Title:	EARLY EXCEPTION DETECTION

Patent #:	8804844	Issue Dt:	08/12/2014	Application #:	11138825	Filing Dt:	05/25/2005
Publication #:	US20050213667	Pub Dt:	09/29/2005
Title:	ADAPTIVE EARLY EXIT TECHNIQUES IN IMAGE CORRELATION

Patent #:	NONE	Issue Dt:		Application #:	11231397	Filing Dt:	09/20/2005
Publication #:	US20060101230	Pub Dt:	05/11/2006
Title:	Maintaining even and odd array pointers to extreme values by searching and comparing multiple elements concurrently where a pointer is adjusted after processing to account for a number of pipeline stages

Patent #:	7360059	Issue Dt:	04/15/2008	Application #:	11347097	Filing Dt:	02/03/2006
Publication #:	US20060149928	Pub Dt:	07/06/2006
Title:	VARIABLE WIDTH ALIGNMENT ENGINE FOR ALIGNING INSTRUCTIONS BASED ON TRANSITION BETWEEN BUFFERS

Assignor

INTEL CORPORATION

Exec Dt:

11/08/2006

Assignee

ANALOG DEVICES, INC.

ONE TECHNOLOGY WAY

P.O. BOX 9106

NORWOOD, MASSACHUSETTS 02062-9106

Correspondence name and address
	SCOTT C. HARRIS
	FISH & RICHARDSON P.C.
	12390 EL CAMINO REAL
	SAN DIEGO, CA 92130

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