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Reel/Frame:018950/0686   Pages: 52
Recorded: 03/02/2007
Attorney Dkt #:10519-206
Conveyance: CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECTIVE MERGER TO ADD PAGES TO THE MERGER DOCUMENT PREVIOUSLY RECORDED PREVIOUSLY RECORDED ON REEL 017544 FRAME 0769. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER.
Total properties: 267
Page 3 of 3
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1
Patent #:
8637366
Issue Dt:
01/28/2014
Application #:
10955549
Filing Dt:
09/29/2004
Publication #:
US20050052915
Pub Dt:
03/10/2005
Title:
NONVOLATILE MEMORY CELL WITHOUT A DIELECTRIC ANTIFUSE HAVING HIGH- AND LOW-IMPEDANCE STATES
2
Patent #:
7566974
Issue Dt:
07/28/2009
Application #:
10955710
Filing Dt:
09/29/2004
Publication #:
US20060071074
Pub Dt:
04/06/2006
Title:
DOPED POLYSILICON VIA CONNECTING POLYSILICON LAYERS
3
Patent #:
7398348
Issue Dt:
07/08/2008
Application #:
10956463
Filing Dt:
09/30/2004
Publication #:
US20060047920
Pub Dt:
03/02/2006
Title:
METHOD AND APPARATUS FOR USING A ONE-TIME OR FEW-TIME PROGRAMMABLE MEMORY WITH A HOST DEVICE DESIGNED FOR ERASABLE/REWRITEABLE MEMORY
4
Patent #:
6996017
Issue Dt:
02/07/2006
Application #:
10961501
Filing Dt:
10/08/2004
Publication #:
US20050044459
Pub Dt:
02/24/2005
Title:
REDUNDANT MEMORY STRUCTURE USING BAD BIT POINTERS
5
Patent #:
7132335
Issue Dt:
11/07/2006
Application #:
10965763
Filing Dt:
10/18/2004
Publication #:
US20050079675
Pub Dt:
04/14/2005
Title:
SEMICONDUCTOR DEVICE WITH LOCALIZED CHARGE STORAGE DIELECTRIC AND METHOD OF MAKING SAME
6
Patent #:
7250646
Issue Dt:
07/31/2007
Application #:
10965780
Filing Dt:
10/18/2004
Publication #:
US20050070060
Pub Dt:
03/31/2005
Title:
TFT MASK ROM AND METHOD FOR MAKING SAME
7
Patent #:
NONE
Issue Dt:
Application #:
10968196
Filing Dt:
10/18/2004
Publication #:
US20060085816
Pub Dt:
04/20/2006
Title:
Method and apparatus to control playback in a download-and-view video on demand system
8
Patent #:
7283403
Issue Dt:
10/16/2007
Application #:
10987091
Filing Dt:
11/12/2004
Publication #:
US20050063220
Pub Dt:
03/24/2005
Title:
MEMORY DEVICE AND METHOD FOR SIMULTANEOUSLY PROGRAMMING AND/OR READING MEMORY CELLS ON DIFFERENT LEVELS
9
Patent #:
6963504
Issue Dt:
11/08/2005
Application #:
10994016
Filing Dt:
11/19/2004
Publication #:
US20050073898
Pub Dt:
04/07/2005
Title:
APPARATUS AND METHOD FOR DISTURB-FREE PROGRAMMING OF PASSIVE ELEMENT MEMORY CELLS
10
Patent #:
7022572
Issue Dt:
04/04/2006
Application #:
10994020
Filing Dt:
11/19/2004
Publication #:
US20050101088
Pub Dt:
05/12/2005
Title:
MANUFACTURING METHOD FOR INTEGRATED CIRCUIT HAVING DISTURB-FREE PROGRAMMING OF PASSIVE ELEMENT MEMORY CELLS
11
Patent #:
7300876
Issue Dt:
11/27/2007
Application #:
11013067
Filing Dt:
12/14/2004
Publication #:
US20060128153
Pub Dt:
06/15/2006
Title:
METHOD FOR CLEANING SLURRY PARTICLES FROM A SURFACE POLISHED BY CHEMICAL MECHANICAL POLISHING
12
Patent #:
7218570
Issue Dt:
05/15/2007
Application #:
11015440
Filing Dt:
12/17/2004
Publication #:
US20060133125
Pub Dt:
06/22/2006
Title:
APPARATUS AND METHOD FOR MEMORY OPERATIONS USING ADDRESS-DEPENDENT CONDITIONS
13
Patent #:
7285464
Issue Dt:
10/23/2007
Application #:
11015824
Filing Dt:
12/17/2004
Publication #:
US20050098800
Pub Dt:
05/12/2005
Title:
NONVOLATILE MEMORY CELL COMPRISING A REDUCED HEIGHT VERTICAL DIODE
14
Patent #:
NONE
Issue Dt:
Application #:
11021238
Filing Dt:
12/23/2004
Publication #:
US20050223243
Pub Dt:
10/06/2005
Title:
Solid-state memory device storing program code and methods for use therewith
15
Patent #:
7277336
Issue Dt:
10/02/2007
Application #:
11024516
Filing Dt:
12/28/2004
Publication #:
US20060140026
Pub Dt:
06/29/2006
Title:
METHOD AND APPARATUS FOR IMPROVING YIELD IN SEMICONDUCTOR DEVICES BY GUARANTEEING HEALTH OF REDUNDANCY INFORMATION
16
Patent #:
7286439
Issue Dt:
10/23/2007
Application #:
11026470
Filing Dt:
12/30/2004
Publication #:
US20060146639
Pub Dt:
07/06/2006
Title:
APPARATUS AND METHOD FOR HIERARCHICAL DECODING OF DENSE MEMORY ARRAYS USING MULTIPLE LEVELS OF MULTIPLE-HEADED DECODERS
17
Patent #:
7177191
Issue Dt:
02/13/2007
Application #:
11026492
Filing Dt:
12/30/2004
Publication #:
US20060146608
Pub Dt:
07/06/2006
Title:
INTEGRATED CIRCUIT INCLUDING MEMORY ARRAY INCORPORATING MULTIPLE TYPES OF NAND STRING STRUCTURES
18
Patent #:
7298665
Issue Dt:
11/20/2007
Application #:
11026493
Filing Dt:
12/30/2004
Publication #:
US20060145193
Pub Dt:
07/06/2006
Title:
DUAL-MODE DECODER CIRCUIT, INTEGRATED CIRCUIT MEMORY ARRAY INCORPORATING SAME, AND RELATED METHODS OF OPERATION
19
Patent #:
NONE
Issue Dt:
Application #:
11040255
Filing Dt:
01/19/2005
Publication #:
US20050158950
Pub Dt:
07/21/2005
Title:
Non-volatile memory cell comprising a dielectric layer and a phase change material in series
20
Patent #:
7465951
Issue Dt:
12/16/2008
Application #:
11040256
Filing Dt:
01/19/2005
Publication #:
US20060157682
Pub Dt:
07/20/2006
Title:
WRITE-ONCE NONVOLATILE PHASE CHANGE MEMORY ARRAY
21
Patent #:
7307268
Issue Dt:
12/11/2007
Application #:
11040262
Filing Dt:
01/19/2005
Publication #:
US20060157679
Pub Dt:
07/20/2006
Title:
STRUCTURE AND METHOD FOR BIASING PHASE CHANGE MEMORY ARRAY FOR RELIABLE WRITING
22
Patent #:
7259038
Issue Dt:
08/21/2007
Application #:
11040465
Filing Dt:
01/19/2005
Publication #:
US20060157683
Pub Dt:
07/20/2006
Title:
FORMING NONVOLATILE PHASE CHANGE MEMORY CELL HAVING A REDUCED THERMAL CONTACT AREA
23
Patent #:
7517796
Issue Dt:
04/14/2009
Application #:
11061952
Filing Dt:
02/17/2005
Publication #:
US20060183282
Pub Dt:
08/17/2006
Title:
METHOD FOR PATTERNING SUBMICRON PILLARS
24
Patent #:
7303959
Issue Dt:
12/04/2007
Application #:
11077901
Filing Dt:
03/11/2005
Publication #:
US20060205124
Pub Dt:
09/14/2006
Title:
BOTTOM-GATE SONOS-TYPE CELL HAVING A SILICIDE GATE
25
Patent #:
7521353
Issue Dt:
04/21/2009
Application #:
11089771
Filing Dt:
03/25/2005
Publication #:
US20060216931
Pub Dt:
09/28/2006
Title:
METHOD FOR REDUCING DIELECTRIC OVERETCH WHEN MAKING CONTACT TO CONDUCTIVE FEATURES
26
Patent #:
7422985
Issue Dt:
09/09/2008
Application #:
11090526
Filing Dt:
03/25/2005
Publication #:
US20060216937
Pub Dt:
09/28/2006
Title:
METHOD FOR REDUCING DIELECTRIC OVERETCH USING A DIELECTRIC ETCH STOP AT A PLANAR SURFACE
27
Patent #:
7359279
Issue Dt:
04/15/2008
Application #:
11095415
Filing Dt:
03/31/2005
Publication #:
US20060221752
Pub Dt:
10/05/2006
Title:
INTEGRATED CIRCUIT MEMORY ARRAY CONFIGURATION INCLUDING DECODING COMPATIBILITY WITH PARTIAL IMPLEMENTATION OF MULTIPLE MEMORY LAYERS
28
Patent #:
7054219
Issue Dt:
05/30/2006
Application #:
11095905
Filing Dt:
03/31/2005
Title:
TRANSISTOR LAYOUT CONFIGURATION FOR TIGHT-PITCHED MEMORY ARRAY LINES
29
Patent #:
7142471
Issue Dt:
11/28/2006
Application #:
11095907
Filing Dt:
03/31/2005
Publication #:
US20060221728
Pub Dt:
10/05/2006
Title:
METHOD AND APPARATUS FOR INCORPORATING BLOCK REDUNDANCY IN A MEMORY ARRAY
30
Patent #:
7553611
Issue Dt:
06/30/2009
Application #:
11097496
Filing Dt:
03/31/2005
Publication #:
US20060222962
Pub Dt:
10/05/2006
Title:
MASKING OF REPEATED OVERLAY AND ALIGNMENT MARKS TO ALLOW REUSE OF PHOTOMASKS IN A VERTICAL STRUCTURE
31
Patent #:
7002825
Issue Dt:
02/21/2006
Application #:
11103184
Filing Dt:
04/11/2005
Publication #:
US20050180244
Pub Dt:
08/18/2005
Title:
WORD LINE ARRANGEMENT HAVING SEGMENTED WORD LINES
32
Patent #:
7177169
Issue Dt:
02/13/2007
Application #:
11103185
Filing Dt:
04/11/2005
Publication #:
US20050180247
Pub Dt:
08/18/2005
Title:
WORD LINE ARRANGEMENT HAVING MULTI-LAYER WORD LINE SEGMENTS FOR THREE-DIMENSIONAL MEMORY ARRAY
33
Patent #:
7106652
Issue Dt:
09/12/2006
Application #:
11103249
Filing Dt:
04/11/2005
Publication #:
US20050180248
Pub Dt:
08/18/2005
Title:
WORD LINE ARRANGEMENT HAVING MULTI-LAYER WORD LINE SEGMENTS FOR THREE-DIMENSIONAL MEMORY ARRAY
34
Patent #:
7236023
Issue Dt:
06/26/2007
Application #:
11106288
Filing Dt:
04/14/2005
Publication #:
US20060232304
Pub Dt:
10/19/2006
Title:
APPARATUS AND METHODS FOR ADAPTIVE TRIP POINT DETECTION
35
Patent #:
NONE
Issue Dt:
Application #:
11125000
Filing Dt:
05/09/2005
Publication #:
US20060250177
Pub Dt:
11/09/2006
Title:
Methods and apparatus for dynamically reconfiguring a charge pump during output transients
36
Patent #:
NONE
Issue Dt:
Application #:
11125606
Filing Dt:
05/09/2005
Publication #:
US20060249753
Pub Dt:
11/09/2006
Title:
High-density nonvolatile memory array fabricated at low temperature comprising semiconductor diodes
37
Patent #:
NONE
Issue Dt:
Application #:
11125939
Filing Dt:
05/09/2005
Publication #:
US20060250836
Pub Dt:
11/09/2006
Title:
Rewriteable memory cell comprising a diode and a resistance-switching material
38
Patent #:
NONE
Issue Dt:
Application #:
11143269
Filing Dt:
06/02/2005
Publication #:
US20060273298
Pub Dt:
12/07/2006
Title:
Rewriteable memory cell comprising a transistor and resistance-switching material in series
39
Patent #:
8110863
Issue Dt:
02/07/2012
Application #:
11143355
Filing Dt:
06/01/2005
Publication #:
US20060273404
Pub Dt:
12/07/2006
Title:
TFT CHARGE STORAGE MEMORY CELL HAVING HIGH-MOBILITY CORRUGATED CHANNEL
40
Patent #:
7272052
Issue Dt:
09/18/2007
Application #:
11146952
Filing Dt:
06/07/2005
Publication #:
US20060221702
Pub Dt:
10/05/2006
Title:
DECODING CIRCUIT FOR NON-BINARY GROUPS OF MEMORY LINE DRIVERS
41
Patent #:
NONE
Issue Dt:
Application #:
11148530
Filing Dt:
06/08/2005
Publication #:
US20050226067
Pub Dt:
10/13/2005
Title:
Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material
42
Patent #:
7764549
Issue Dt:
07/27/2010
Application #:
11157293
Filing Dt:
06/20/2005
Publication #:
US20060285422
Pub Dt:
12/21/2006
Title:
FLOATING BODY MEMORY CELL SYSTEM AND METHOD OF MANUFACTURE
43
Patent #:
7317641
Issue Dt:
01/08/2008
Application #:
11157317
Filing Dt:
06/20/2005
Publication #:
US20060285423
Pub Dt:
12/21/2006
Title:
VOLATILE MEMORY CELL TWO-PASS WRITING METHOD
44
Patent #:
7212454
Issue Dt:
05/01/2007
Application #:
11158396
Filing Dt:
06/22/2005
Publication #:
US20060291303
Pub Dt:
12/28/2006
Title:
METHOD AND APPARATUS FOR PROGRAMMING A MEMORY ARRAY
45
Patent #:
7678420
Issue Dt:
03/16/2010
Application #:
11159031
Filing Dt:
06/22/2005
Publication #:
US20060292301
Pub Dt:
12/28/2006
Title:
METHOD OF DEPOSITING GERMANIUM FILMS
46
Patent #:
NONE
Issue Dt:
Application #:
11173973
Filing Dt:
07/01/2005
Publication #:
US20070069241
Pub Dt:
03/29/2007
Title:
Memory with high dielectric constant antifuses and method for using at low voltage
47
Patent #:
7304888
Issue Dt:
12/04/2007
Application #:
11174234
Filing Dt:
07/01/2005
Publication #:
US20070002610
Pub Dt:
01/04/2007
Title:
REVERSE-BIAS METHOD FOR WRITING MEMORY CELLS IN A MEMORY ARRAY
48
Patent #:
7453755
Issue Dt:
11/18/2008
Application #:
11174240
Filing Dt:
07/01/2005
Publication #:
US20070002603
Pub Dt:
01/04/2007
Title:
MEMORY CELL WITH HIGH-K ANTIFUSE FOR REVERSE BIAS PROGRAMMING
49
Patent #:
NONE
Issue Dt:
Application #:
11175688
Filing Dt:
07/06/2005
Publication #:
US20070007577
Pub Dt:
01/11/2007
Title:
INTEGRATED CIRCUIT EMBODYING A NON-VOLATILE MEMORY CELL
50
Patent #:
7362604
Issue Dt:
04/22/2008
Application #:
11179077
Filing Dt:
07/11/2005
Publication #:
US20070008785
Pub Dt:
01/11/2007
Title:
APPARATUS AND METHOD FOR PROGRAMMING AN ARRAY OF NONVOLATILE MEMORY CELLS INCLUDING SWITCHABLE RESISTOR MEMORY ELEMENTS
51
Patent #:
NONE
Issue Dt:
Application #:
11179095
Filing Dt:
07/11/2005
Publication #:
US20070007579
Pub Dt:
01/11/2007
Title:
Memory cell comprising a thin film three-terminal switching device having a metal source and /or drain region
52
Patent #:
7426128
Issue Dt:
09/16/2008
Application #:
11179122
Filing Dt:
07/11/2005
Publication #:
US20070008773
Pub Dt:
01/11/2007
Title:
SWITCHABLE RESISTIVE MEMORY WITH OPPOSITE POLARITY WRITE PULSES
53
Patent #:
7345907
Issue Dt:
03/18/2008
Application #:
11179123
Filing Dt:
07/11/2005
Publication #:
US20070008786
Pub Dt:
01/11/2007
Title:
APPARATUS AND METHOD FOR READING AN ARRAY OF NONVOLATILE MEMORY CELLS INCLUDING SWITCHABLE RESISTOR MEMORY ELEMENTS
54
Patent #:
7280397
Issue Dt:
10/09/2007
Application #:
11179360
Filing Dt:
07/11/2005
Publication #:
US20070008776
Pub Dt:
01/11/2007
Title:
THREE-DIMENSIONAL NON-VOLATILE SRAM INCORPORATING THIN-FILM DEVICE LAYER
55
Patent #:
NONE
Issue Dt:
Application #:
11179423
Filing Dt:
07/11/2005
Publication #:
US20070010100
Pub Dt:
01/11/2007
Title:
Method of plasma etching transition metals and their compounds
56
Patent #:
7265049
Issue Dt:
09/04/2007
Application #:
11215951
Filing Dt:
08/31/2005
Publication #:
US20060006495
Pub Dt:
01/12/2006
Title:
ULTRATHIN CHEMICALLY GROWN OXIDE FILM AS A DOPANT DIFFUSION BARRIER IN SEMICONDUCTOR DEVICES
57
Patent #:
7276403
Issue Dt:
10/02/2007
Application #:
11237162
Filing Dt:
09/28/2005
Publication #:
US20060024868
Pub Dt:
02/02/2006
Title:
SELECTIVE OXIDATION OF SILICON IN DIODE, TFT, AND MONOLITHIC THREE DIMENSIONAL MEMORY ARRAYS
58
Patent #:
7800932
Issue Dt:
09/21/2010
Application #:
11237167
Filing Dt:
09/28/2005
Publication #:
US20070090425
Pub Dt:
04/26/2007
Title:
MEMORY CELL COMPRISING SWITCHABLE SEMICONDUCTOR MEMORY ELEMENT WITH TRIMMABLE RESISTANCE
59
Patent #:
7238607
Issue Dt:
07/03/2007
Application #:
11237169
Filing Dt:
09/28/2005
Publication #:
US20060054962
Pub Dt:
03/16/2006
Title:
METHOD TO MINIMIZE FORMATION OF RECESS AT SURFACE PLANARIZED BY CHEMICAL MECHANICAL PLANARIZATION
60
Patent #:
NONE
Issue Dt:
Application #:
11249212
Filing Dt:
10/13/2005
Publication #:
US20060033180
Pub Dt:
02/16/2006
Title:
Low-density, high-resistivity titanium nitride layer for use as a contact for low-leakage dielectric layers and method of making
61
Patent #:
NONE
Issue Dt:
Application #:
11271078
Filing Dt:
11/10/2005
Publication #:
US20070102724
Pub Dt:
05/10/2007
Title:
Vertical diode doped with antimony to avoid or limit dopant diffusion
62
Patent #:
7816659
Issue Dt:
10/19/2010
Application #:
11287452
Filing Dt:
11/23/2005
Publication #:
US20070114508
Pub Dt:
05/24/2007
Title:
DEVICES HAVING REVERSIBLE RESISTIVITY-SWITCHING METAL OXIDE OR NITRIDE LAYER WITH ADDED METAL
63
Patent #:
7291562
Issue Dt:
11/06/2007
Application #:
11298015
Filing Dt:
12/09/2005
Publication #:
US20070134923
Pub Dt:
06/14/2007
Title:
METHOD TO FORM TOPOGRAPHY IN A DEPOSITED LAYER ABOVE A SUBSTRATE
64
Patent #:
7405465
Issue Dt:
07/29/2008
Application #:
11298331
Filing Dt:
12/09/2005
Publication #:
US20060087005
Pub Dt:
04/27/2006
Title:
DEPOSITED SEMICONDUCTOR STRUCTURE TO MINIMIZE N-TYPE DOPANT DIFFUSION AND METHOD OF MAKING
65
Patent #:
7615502
Issue Dt:
11/10/2009
Application #:
11303229
Filing Dt:
12/16/2005
Publication #:
US20070141858
Pub Dt:
06/21/2007
Title:
LASER ANNEAL OF VERTICALLY ORIENTED SEMICONDUCTOR STRUCTURES WHILE MAINTAINING A DOPANT PROFILE
66
Patent #:
7265000
Issue Dt:
09/04/2007
Application #:
11354470
Filing Dt:
02/14/2006
Publication #:
US20060134837
Pub Dt:
06/22/2006
Title:
VERTICALLY STACKED FIELD PROGRAMMABLE NONVOLATILE MEMORY AND METHOD OF FABRICATION
67
Patent #:
7319053
Issue Dt:
01/15/2008
Application #:
11355214
Filing Dt:
02/14/2006
Publication #:
US20060141679
Pub Dt:
06/29/2006
Title:
VERTICALLY STACKED FIELD PROGRAMMABLE NONVOLATILE MEMORY AND METHOD OF FABRICATION
Assignor
1
MATRIX SEMICONDUCTOR, INC.
Exec Dt:
10/20/2005
Assignee
1
SANDISK 3D LLC
140 CASPIAN COURT
SUNNYVALE, CALIFORNIA 94089
Correspondence name and address
BRINKS HOFER GILSON & LIONE
P.O. BOX 10395
CHICAGO, IL 60610

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