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Patent Assignment Details
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Reel/Frame:019028/0599   Pages: 6
Recorded: 03/19/2007
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 35
1
Patent #:
5335198
Issue Dt:
08/02/1994
Application #:
08057583
Filing Dt:
05/06/1993
Title:
FLASH EEPROM ARRAY WITH HIGH ENDURANCE
2
Patent #:
5367206
Issue Dt:
11/22/1994
Application #:
08078711
Filing Dt:
06/17/1993
Title:
OUTPUT BUFFER CIRCUIT FOR A LOW VOLTAGE EPROM Q
3
Patent #:
5357458
Issue Dt:
10/18/1994
Application #:
08083736
Filing Dt:
06/25/1993
Title:
SYSTEM FOR ALLOWING A CONTENT ADDRESSABLE MEMORY TO OPERATE WITH MULTIPLE POWER VOLTAGE LEVELS
4
Patent #:
5406517
Issue Dt:
04/11/1995
Application #:
08109881
Filing Dt:
08/23/1993
Title:
DISTRIBUTED NEGATIVE GATE POWER SUPPLY
5
Patent #:
5365484
Issue Dt:
11/15/1994
Application #:
08109887
Filing Dt:
08/23/1993
Title:
INDEPENDENT ARRAY GROUNDS FOR FLASH EEPROM ARRAY WITH PAGED ERASE ARCHITECTURE
6
Patent #:
5349558
Issue Dt:
09/20/1994
Application #:
08112033
Filing Dt:
08/26/1993
Title:
SECTOR-BASED REDUNDANCY ARCHITECTURE
7
Patent #:
5511026
Issue Dt:
04/23/1996
Application #:
08160578
Filing Dt:
12/01/1993
Title:
BOOSTED AND REGULATED GATE POWER SUPPLY WITH REFERENCE TRACKING FOR MULTI-DENSITY AND LOW VOLTAGE SUPPLY MEMORIES
8
Patent #:
5828601
Issue Dt:
10/27/1998
Application #:
08160582
Filing Dt:
12/01/1993
Title:
PROGRAMMED REFERENCE
9
Patent #:
5530803
Issue Dt:
06/25/1996
Application #:
08227755
Filing Dt:
04/14/1994
Title:
METHOD AND APPARATUS FOR PROGRAMMING MEMORY DEVICES
10
Patent #:
5470773
Issue Dt:
11/28/1995
Application #:
08233174
Filing Dt:
04/25/1994
Title:
METHOD PROTECTING A STACKED GATE EDGE IN A SEMICONDUCTOR DEVICE FROM SELF ALIGNED SOURCE (SAS) ETCH
11
Patent #:
5955874
Issue Dt:
09/21/1999
Application #:
08265583
Filing Dt:
06/23/1994
Title:
SUPPLY VOLTAGE-INDEPENDENT REFERENCE VOLTAGE CIRCUIT
12
Patent #:
5541875
Issue Dt:
07/30/1996
Application #:
08269478
Filing Dt:
07/01/1994
Title:
HIGH ENERGY BURIED LAYER IMPLANT TO PROVIDE A LOW RESISTANCE P-WELL IN A FLASH EPROM ARRAY
13
Patent #:
5576991
Issue Dt:
11/19/1996
Application #:
08269540
Filing Dt:
07/01/1994
Title:
MULTISTEPPED THRESHOLD CONVERGENCE FOR A FLASH MEMORY ARRAY
14
Patent #:
5468981
Issue Dt:
11/21/1995
Application #:
08299868
Filing Dt:
09/01/1994
Title:
SELF-ALIGNED BURIED CHANNEL/JUNCTION STACKED GATE FLASH MEMORY CELL
15
Patent #:
5574685
Issue Dt:
11/12/1996
Application #:
08299876
Filing Dt:
09/01/1994
Title:
SELF-ALIGNED BURIED CHANNEL/JUNCTION STACKED GATE FLASH MEMORY CELL
16
Patent #:
5485423
Issue Dt:
01/16/1996
Application #:
08320368
Filing Dt:
10/11/1994
Title:
METHOD FOR ELIMINATING OF CYCLING-INDUCED ELECTRON TRAPPING IN THE TUNNELING OXIDE OF 5 VOLT ONLY FLASH EEPROMS
17
Patent #:
5457336
Issue Dt:
10/10/1995
Application #:
08322811
Filing Dt:
10/13/1994
Title:
NON-VOLATILE MEMORY STRUCTURE INCLUDING PROTECTION AND STRUCTURE FOR MAINTAINING THRESHOLD STABILITY
18
Patent #:
5534731
Issue Dt:
07/09/1996
Application #:
08330871
Filing Dt:
10/28/1994
Title:
LAYERED LOW DIELECTRIC CONSTANT TECHNOLOGY
19
Patent #:
5550405
Issue Dt:
08/27/1996
Application #:
08360856
Filing Dt:
12/21/1994
Title:
NOVEL PROCESSING TECHNIQUES FOR ACHIEVING PRODUCTION-WORTHY, LOW DIELECTRIC, LOW INTERCONNECT RESISTANCE AND HIGH PERFORMANCE ICS
20
Patent #:
5481494
Issue Dt:
01/02/1996
Application #:
08362346
Filing Dt:
12/22/1994
Title:
METHOD FOR TIGHTENING VT DISTRIBUTION OF 5 VOLT-ONLY FLASH EEPROMS
21
Patent #:
5656521
Issue Dt:
08/12/1997
Application #:
08371704
Filing Dt:
01/12/1995
Title:
METHOD OF ERASING UPROM TRANSISTORS
22
Patent #:
5491657
Issue Dt:
02/13/1996
Application #:
08393636
Filing Dt:
02/24/1995
Title:
METHODS FOR BULK (OR BYTE) CHARGING AND DISCHARGING AN ARRAY OF FLASH EEPROM MEMORY CELLS
23
Patent #:
5482881
Issue Dt:
01/09/1996
Application #:
08403460
Filing Dt:
03/14/1995
Title:
METHOD OF MAKING FLASH EEPROM MEMORY WITH REDUCED COLUMN LEAKAGE CURRENT
24
Patent #:
5617357
Issue Dt:
04/01/1997
Application #:
08420989
Filing Dt:
04/07/1995
Title:
FLASH EEPROM MEMORY WITH IMPROVED DISCHARGE SPEED USING SUBSTRATE BIAS AND METHOD THEREFOR
25
Patent #:
5534455
Issue Dt:
07/09/1996
Application #:
08433267
Filing Dt:
05/02/1995
Title:
METHOD FOR PROTECTING A STACKED GATE EDGE IN A SEMICONDUCTOR DEVICE FROM SELF ALIGNED SOURCE (SAS) ETCH
26
Patent #:
5693566
Issue Dt:
12/02/1997
Application #:
08459957
Filing Dt:
06/02/1995
Title:
LAYERED LOW DIELECTRIC CONSTANT TECHNOLOGY
27
Patent #:
5517443
Issue Dt:
05/14/1996
Application #:
08460603
Filing Dt:
06/01/1995
Title:
METHOD AND SYSTEM FOR PROTECTING A STACKED GATE EDGE IN A SEMI- CONDUCTOR DEVICE FROM SELF ALIGNED SOURCE (SAS) ETCH IN A SEMI- CONDUCTOR DEVICE
28
Patent #:
5679608
Issue Dt:
10/21/1997
Application #:
08463448
Filing Dt:
06/05/1995
Title:
NOVEL PROCESSING TECHNIQUES FOR ACHIEVING PRODUCTION-WORTHY, LOW DIELECTRIC, LOW INTERCONNECT RESISTANCE AND HIGH PERFORMANCE IC
29
Patent #:
5598369
Issue Dt:
01/28/1997
Application #:
08484252
Filing Dt:
06/07/1995
Title:
FLASH EEPROM ARRAY WITH FLOATING SUBSTRATE ERASE OPERATION
30
Patent #:
5561620
Issue Dt:
10/01/1996
Application #:
08508425
Filing Dt:
07/31/1995
Title:
FLASH EEPROM ARRAY WITH FLOATING SUBSTRATE ERASE OPERATION
31
Patent #:
5726920
Issue Dt:
03/10/1998
Application #:
08537116
Filing Dt:
09/29/1995
Title:
WATCHDOG SYSTEM HAVING DATA DIFFERENTIATING MEANS FOR USE IN MONITORING OF SEMICONDUCTOR WAFER TESTING LINE
32
Patent #:
5965934
Issue Dt:
10/12/1999
Application #:
08681141
Filing Dt:
07/22/1996
Title:
NOVEL PROCESSING TECHNIQUES FOR ACHIEVING PRODUCTION-WORTHY, LOW DIELECTRIC, LOW INTERCONNECT RESISTANCE AND HIGH PERFORMANCE ICS
33
Patent #:
5652447
Issue Dt:
07/29/1997
Application #:
08684920
Filing Dt:
07/22/1996
Title:
A FLASH EEPROM MEMORY WITH REDUCED COLUMN LEAKAGE CURRENT AND METHOD THEREFOR
34
Patent #:
6593245
Issue Dt:
07/15/2003
Application #:
08690848
Filing Dt:
08/01/1996
Title:
SILICON NITRIDE ETCH PROCESS WITH CRITICAL GAIN
35
Patent #:
5693972
Issue Dt:
12/02/1997
Application #:
08769178
Filing Dt:
12/18/1996
Title:
SEMICONDUCTOR DEVICE FROM SELF-ALIGNED SOURCE (SAS) ETCH IN A SEMICONDUCTOR DEVICE
Assignor
1
ADVANCED MICRO DEVICES, INC.
Exec Dt:
01/31/2007
Assignee
1
SPANSION INC.
915 DEGUIGNE DRIVE, P.O. BOX 3453
MAIL STOP 250
SUNNYVALE, CALIFORNIA 94088-3453
Correspondence name and address
RAYMOND E. FRITZ
915 DEGUIGNE DRIVE, P.O. BOX 3453
MAIL STOP 250
SUNNYVALE, CA 94088-3453

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