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Patent Assignment Details
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Reel/Frame:019028/0644   Pages: 6
Recorded: 03/19/2007
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 35
1
Patent #:
Issue Dt:
10/03/2000
Application #:
08991687
Filing Dt:
12/16/1997
Title:
NON-SELF-ALIGNED SIDE CHANNEL IMPLANTS FOR FLASH MEMORY CELLS
2
Patent #:
Issue Dt:
05/14/2002
Application #:
08992616
Filing Dt:
12/17/1997
Title:
METHOD AND SYSTEM FOR PROVIDING LOCALIZED GATE EDGE ROUNDING WITH MINIMAL ENCROACHMENT AND GATE EDGE LIFTING
3
Patent #:
Issue Dt:
08/15/2000
Application #:
08992618
Filing Dt:
12/17/1997
Title:
METHOD AND SYSTEM FOR PROVIDING A DRAIN SIDE POCKET IMPLANT
4
Patent #:
Issue Dt:
09/07/1999
Application #:
08992622
Filing Dt:
12/17/1997
Title:
METHOD AND SYSTEM FOR SELECTED SOURCE DURING READ AND PROGRAMMING OF FLASH MEMORY
5
Patent #:
Issue Dt:
11/30/1999
Application #:
08993343
Filing Dt:
12/18/1997
Title:
MANUFACTURING PROCESS TO ELIMINATE POLYSTRINGERS IN HIGH DENSITY NAND-TYPE FLASH MEMORY DEVICES
6
Patent #:
Issue Dt:
08/28/2001
Application #:
08993344
Filing Dt:
12/18/1997
Title:
MANUFACTURING PROCESS TO ELIMINATE ONO FENCE MATERIAL IN HIGH DENSITY NAND-TYPE FLASH MEMORY DEVICES
7
Patent #:
Issue Dt:
09/05/2000
Application #:
08993443
Filing Dt:
12/18/1997
Title:
NITROGEN ION IMPLANTED AMORPHOUS SILICON TO PRODUCE OXIDATION RESISTANT AND FINER GRAIN POLYSILICON BASED FLOATING GATES
8
Patent #:
Issue Dt:
10/31/2000
Application #:
08993444
Filing Dt:
12/18/1997
Title:
IN SITU P DOPED AMORPHOUS SILICON BY NH3 TO FORM OXIDATION RESISTANT AND FINER GRAIN FLOATING GATES.
9
Patent #:
Issue Dt:
08/17/1999
Application #:
08993599
Filing Dt:
12/18/1997
Title:
METHOD AND SYSTEM FOR SOURCE ONLY REOXIDATION AFTER JUNCTION IMPLANT FOR FLASH MEMORY DEVICES
10
Patent #:
Issue Dt:
02/15/2000
Application #:
08993600
Filing Dt:
12/18/1997
Title:
METHOD AND SYSTEM FOR USING A SPACER TO OFFSET IMPLANT DAMAGE AND REDUCE LATERAL DIFFUSION IN FLASH MEMORY DEVICES
11
Patent #:
Issue Dt:
12/21/1999
Application #:
08993634
Filing Dt:
12/18/1997
Title:
SPLIT VOLTAGE FOR NAND FLASH
12
Patent #:
Issue Dt:
01/18/2000
Application #:
08993787
Filing Dt:
12/19/1997
Title:
METHOD AND SYSTEM FOR GATE STACK REOXIDATION CONTROL
13
Patent #:
Issue Dt:
12/11/2001
Application #:
08994140
Filing Dt:
12/19/1997
Title:
METHOD FOR LATERALLY PEAKED SOURCE DOPING PROFILES FOR BETTER ERASE CONTROL IN FLASH MEMORY DEVICES
14
Patent #:
Issue Dt:
02/13/2001
Application #:
09006757
Filing Dt:
01/14/1998
Title:
FLASH EPROM CELL WITH REDUCED SHORT CHANNEL EFFECT AND METHOD FOR PROVIDING SAME
15
Patent #:
Issue Dt:
03/30/1999
Application #:
09023241
Filing Dt:
02/13/1998
Title:
NON-UNIFORM THRESHOLD VOLTAGE ADJUSTMENT IN FLASH EPROMS THROUGH GATE WORK FUNCTION ALTERATION
16
Patent #:
Issue Dt:
10/24/2000
Application #:
09023497
Filing Dt:
02/13/1998
Title:
FLOATING GATE CAPACITOR FOR USE IN VOLTAGE REGULATORS
17
Patent #:
Issue Dt:
11/28/2000
Application #:
09040107
Filing Dt:
03/17/1998
Title:
NEW APPROACH FOR THE FORMATION OF SEMICONDUCTOR DEVICES WHICH REDUCES BAND-TO-BAND TUNNELING CURRENT AND SHORT-CHANNEL EFFECTS
18
Patent #:
Issue Dt:
11/09/1999
Application #:
09045013
Filing Dt:
03/20/1998
Title:
NARROWER ERASE DISTRIBUTION FOR FLASH MEMORY BY SMALLER POLY GRAIN SIZE
19
Patent #:
Issue Dt:
07/17/2001
Application #:
09047237
Filing Dt:
03/25/1998
Title:
CAPACITOR FOR USE IN A CAPACITOR DIVIDER THAT HAS A FLOATING GATE TRANSISTOR AS A CORRESPONDING CAPACITOR
20
Patent #:
Issue Dt:
05/04/1999
Application #:
09085552
Filing Dt:
05/27/1998
Title:
METHOD FOR ERASING FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY (EEPROM )
21
Patent #:
Issue Dt:
12/05/2000
Application #:
09085680
Filing Dt:
05/27/1998
Title:
METHOD FOR ERASING FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY(EEPROM)
22
Patent #:
Issue Dt:
02/23/1999
Application #:
09085705
Filing Dt:
05/27/1998
Title:
METHOD FOR PROGRAMMING FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
23
Patent #:
Issue Dt:
05/16/2000
Application #:
09098292
Filing Dt:
06/16/1998
Title:
RTCVD OXIDE AND N2O ANNEAL FOR TOP OXIDE OF ONO FILM
24
Patent #:
Issue Dt:
01/04/2000
Application #:
09132347
Filing Dt:
08/12/1998
Title:
METHOD FOR SENSING STATE OF ERASURE OF A FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY (EEPROM)
25
Patent #:
Issue Dt:
04/18/2000
Application #:
09132981
Filing Dt:
08/12/1998
Title:
METHOD FOR TIGHTENING ERASE THRESHOLD VOLTAGE DISTRIBUTION IN FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY (EEPROM)
26
Patent #:
Issue Dt:
11/23/1999
Application #:
09161423
Filing Dt:
09/24/1998
Title:
METHOD FOR REDUCING PROGRAM DISTURB DURING SELF-BOOSTING IN A NAND FLASH MEMORY
27
Patent #:
Issue Dt:
03/20/2001
Application #:
09166384
Filing Dt:
10/05/1998
Title:
METHOD FOR ERASING FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY (EEPROM)
28
Patent #:
Issue Dt:
01/23/2001
Application #:
09177817
Filing Dt:
10/23/1998
Title:
HIGH VOLTAGE TRANSISTOR WITH HIGH GATED DIODE BREAKDOWN VOLTAGE
29
Patent #:
Issue Dt:
06/27/2000
Application #:
09232023
Filing Dt:
01/14/1999
Title:
EEPROM DECODER BLOCK HAVING A P-WELL COUPLED TO A CHARGE PUMP FOR CHARGING THE P-WELL AND METHOD OF PROGRAMMING WITH THE EEPROM DECODER BLOCK
30
Patent #:
Issue Dt:
04/24/2001
Application #:
09257733
Filing Dt:
02/25/1999
Title:
USE OF IMPLANTED IONS TO REDUCE OXIDE-NITRIDE-OXIDE (ONO) ETCH RESIDUE AND POLYSTRINGERS
31
Patent #:
Issue Dt:
01/09/2001
Application #:
09404078
Filing Dt:
09/23/1999
Title:
CONCURRENT ERASE VERIFY SCHEME FOR FLASH MEMORY APPLICATIONS
32
Patent #:
Issue Dt:
09/19/2000
Application #:
09413182
Filing Dt:
10/05/1999
Title:
BIT BY BIT APDE VERIFY FOR FLASH MEMORY APPLICATIONS
33
Patent #:
Issue Dt:
08/14/2001
Application #:
09416563
Filing Dt:
10/12/1999
Title:
MULTIPLE BYTE CHANNEL HOT ELECTRON PROGRAMMING USING RAMPED GATE AND SOURCE BIAS VOLTAGE
34
Patent #:
Issue Dt:
04/04/2000
Application #:
09417273
Filing Dt:
10/13/1999
Title:
CIRCUIT IMPLEMENTATION TO QUENCH BIT LINE LEAKAGE CURRENT IN PROGRAMMING AND OVER-ERASE CORRECTION MODES IN FLASH EEPROM
35
Patent #:
Issue Dt:
06/25/2002
Application #:
09478864
Filing Dt:
01/07/2000
Title:
METHOD AND SYSTEM FOR USING A SPACER TO OFFSET IMPLANT DAMAGE AND REDUCE LATERAL DIFFUSION IN FLASH MEMORY DEVICES
Assignor
1
Exec Dt:
01/31/2007
Assignee
1
915 DEGUIGNE DRIVE, P.O. BOX 3453
MAIL STOP 250
SUNNYVALE, CALIFORNIA 94088-3453
Correspondence name and address
RAYMOND E. FRITZ
915 DEGUIGNE DRIVE, P.O. BOX 3453
MAIL STOP 250
SUNNYVALE, CA 94088-3453

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