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Total properties:
21
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Patent #:
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Issue Dt:
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05/22/2012
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Application #:
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09539458
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Filing Dt:
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03/30/2000
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Title:
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METHOD AND SYSTEM FOR PROVIDING CONTACT TO A FIRST POLYSILICON LAYER IN A FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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06/21/2011
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Application #:
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09591266
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Filing Dt:
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06/09/2000
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Title:
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ANTI-REFLECTIVE INTERPOLY DIELECTRIC
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09667347
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Filing Dt:
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09/22/2000
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Title:
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Serial sequencing of automatic program disturb erase verify during a fast erase mode
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Patent #:
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Issue Dt:
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05/15/2007
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Application #:
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09805273
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Filing Dt:
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03/13/2001
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Title:
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A METHOD OF FORMING HIGHLY CONDUCTIVE SEMICONDUCTOR STRUCTURES VIA PLASMA ETCH
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Patent #:
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Issue Dt:
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04/24/2007
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Application #:
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10151595
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Filing Dt:
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05/16/2002
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Title:
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SEMICONDUCTOR DEVICE WITH HIGH CONDUCTIVITY REGION USING SHALLOW TRENCH
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10155767
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Filing Dt:
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05/24/2002
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Publication #:
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Pub Dt:
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11/27/2003
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Title:
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Stepped pre-erase voltages for mirrorbit erase
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Patent #:
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Issue Dt:
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03/02/2010
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Application #:
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10273184
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Filing Dt:
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10/18/2002
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Title:
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NITRIDATION OF GATE OXIDE BY LASER PROCESSING
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Patent #:
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Issue Dt:
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10/21/2008
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Application #:
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10277395
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Filing Dt:
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10/22/2002
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Publication #:
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Pub Dt:
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09/18/2003
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Title:
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SHALLOW TRENCH ISOLATION APPROACH FOR IMPROVED STI CORNER ROUNDING
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Patent #:
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Issue Dt:
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05/22/2007
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Application #:
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10314591
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Filing Dt:
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12/09/2002
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Publication #:
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Pub Dt:
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06/10/2004
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Title:
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SELF ALIGNED MEMORY ELEMENT AND WORDLINE
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Patent #:
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Issue Dt:
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06/19/2007
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Application #:
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10431321
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Filing Dt:
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05/06/2003
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Title:
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A METHOD FOR MANUFACTURING A DOUBLE BITLINE IMPLANT
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
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10689298
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Filing Dt:
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10/20/2003
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Publication #:
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Pub Dt:
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04/29/2004
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Title:
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Method and system for reducing short channel effects in a memory device by reduction of drain thermal cycling
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10817131
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Filing Dt:
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04/02/2004
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Publication #:
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Pub Dt:
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10/13/2005
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Title:
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In-situ surface treatment for memory cell formation
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Patent #:
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Issue Dt:
|
03/03/2009
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Application #:
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10817186
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Filing Dt:
|
04/02/2004
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Title:
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USING ORGANIC SEMICONDUCTOR MEMORY IN CONJUNCTION WITH A MEMS ACTUATOR FOR AN ULTRA HIGH DENSITY MEMORY
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|
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Patent #:
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Issue Dt:
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10/27/2009
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Application #:
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10817467
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Filing Dt:
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04/02/2004
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Publication #:
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Pub Dt:
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10/13/2005
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Title:
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POLYMER DIELECTRICS FOR MEMORY ELEMENT ARRAY INTERCONNECT
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Patent #:
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|
Issue Dt:
|
04/08/2014
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Application #:
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10927692
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Filing Dt:
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08/27/2004
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Title:
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MEMORY DEVICES CONTAINING A HIGH-K DIELECTRIC LAYER
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Patent #:
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Issue Dt:
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05/20/2008
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Application #:
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10978845
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Filing Dt:
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11/01/2004
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Title:
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METHOD OF MAKING AN ORGANIC MEMORY CELL
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Patent #:
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Issue Dt:
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10/28/2008
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Application #:
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10983919
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Filing Dt:
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11/08/2004
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Publication #:
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Pub Dt:
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03/30/2006
| | | | |
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Title:
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CONTROL OF MEMORY DEVICES POSSESSING VARIABLE RESISTANCE CHARACTERISTICS
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Patent #:
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NONE
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Issue Dt:
|
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Application #:
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11000685
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Filing Dt:
|
12/01/2004
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Publication #:
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Pub Dt:
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06/01/2006
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Title:
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Polymer-based transistor devices, methods, and systems
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|
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Patent #:
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|
Issue Dt:
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09/25/2007
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Application #:
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11034071
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Filing Dt:
|
01/12/2005
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Title:
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VARIABLE DENSITY AND VARIABLE PERSISTENT ORGANIC MEMORY DEVICES, METHODS, AND FABRICATION
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|
|
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Patent #:
|
|
Issue Dt:
|
01/29/2008
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Application #:
|
11102004
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Filing Dt:
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04/08/2005
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Title:
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ETCH-BACK PROCESS FOR CAPPING A POLYMER MEMORY DEVICE
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|
|
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Patent #:
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|
Issue Dt:
|
12/16/2008
|
Application #:
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11251999
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Filing Dt:
|
10/17/2005
|
|
Title:
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STACKED ORGANIC MEMORY DEVICES AND METHODS OF OPERATING AND FABRICATING
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