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Total properties:
35
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Patent #:
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Issue Dt:
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03/12/2002
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Application #:
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09657029
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Filing Dt:
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09/07/2000
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Title:
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Using negative gate erase voltage to simultaneously erase two bits from a non-volatile memory cell with an oxide-nitride-oxide (ONO) gate structure
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09657143
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Filing Dt:
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09/07/2000
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Title:
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USING A NEGATIVE GATE ERASE VOLTAGE APPLIED IN STEPS OF DECREASING AMOUNTS TO REDUCE ERASE TIME FOR A NON-VOLATILE MEMORY CELL WITH AN OXIDE-NITRIDE-OXIDE (ONO) STRUCTURE
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Patent #:
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Issue Dt:
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12/31/2002
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Application #:
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09699531
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Filing Dt:
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10/30/2000
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Title:
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METHOD FOR SELECTIVE REMOVAL OF ONO LAYER
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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09699711
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Filing Dt:
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10/30/2000
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Title:
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SOURCE SIDE BORON IMPLANT AND DRAIN SIDE MDD IMPLANT FOR DEEP SUB 0.18 MICRON FLASH MEMORY
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Patent #:
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Issue Dt:
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02/17/2004
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Application #:
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09713390
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Filing Dt:
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11/15/2000
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Title:
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FLASH MEMORY CELL WITH MINIMIZED FLOATING GATE TO DRAIN/SOURCE OVERLAP FOR MINIMIZING CHARGE LEAKAGE
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Patent #:
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Issue Dt:
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10/23/2001
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Application #:
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09716659
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Filing Dt:
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11/20/2000
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Title:
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Double layer hard mask process to improve oxide quality for non-volatile flash memory products
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Patent #:
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Issue Dt:
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08/31/2004
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Application #:
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09732616
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Filing Dt:
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12/07/2000
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Title:
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INTERNAL SELF-TEST CIRCUIT FOR A MEMORY ARRAY
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Patent #:
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Issue Dt:
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01/27/2004
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Application #:
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09733252
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Filing Dt:
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12/07/2000
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Title:
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RELIABILITY MONITOR FOR A MEMORY ARRAY
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Patent #:
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Issue Dt:
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07/09/2002
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Application #:
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09779225
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Filing Dt:
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02/08/2001
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Title:
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PIGGYBACK PROGRAMMING USING GRADUATED STEPS FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
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Patent #:
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Issue Dt:
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12/17/2002
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Application #:
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09779764
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Filing Dt:
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02/08/2001
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Title:
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CONCURRENT PROGRAM RECONNAISSANCE WITH PIGGYBACK PULSES FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09779792
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Filing Dt:
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02/08/2001
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Title:
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PIGGYBACK PROGRAMMING USING TIMING CONTROL FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
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Patent #:
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Issue Dt:
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04/22/2003
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Application #:
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09779794
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Filing Dt:
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02/08/2001
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Title:
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PIGGYBACK PROGRAMMING USING AN EXTENDED FIRST PULSE FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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09779821
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Filing Dt:
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02/08/2001
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Title:
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PIGGYBACK PROGRAMMING USING VOLTAGE CONTROL FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
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Patent #:
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Issue Dt:
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07/23/2002
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Application #:
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09779864
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Filing Dt:
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02/08/2001
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Title:
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PROGRAM RECONNAISSANCE TO ELIMINATE VARIATIONS IN VT DISTRIBUTIONS OF MULTI-LEVEL CELL FLASH MEMORY DESIGNS
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Patent #:
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Issue Dt:
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12/30/2003
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Application #:
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09779884
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Filing Dt:
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02/08/2001
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Title:
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PIGGYBACK PROGRAMMING WITH STAIRCASE VERIFY FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
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Patent #:
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Issue Dt:
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12/03/2002
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Application #:
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09788045
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Filing Dt:
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02/16/2001
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Title:
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METHOD OF FORMING A VOID-FREE INTERLAYER DIELECTRIC (ILD0) FOR 0.18-UM FLASH MEMORY TECHNOLOGY AND SEMICONDUCTOR DEVICE THEREBY FORMED
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Patent #:
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Issue Dt:
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09/17/2002
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Application #:
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09794478
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Filing Dt:
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02/26/2001
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Title:
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ADDRESS BROADCASTING TO A PAGED MEMORY DEVICE TO ELIMINATE ACCESS LATENCY PENALTY
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09794479
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Filing Dt:
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02/26/2001
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Title:
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CONFIGURE REGISTERS AND LOADS TO TAILOR A MULTI-LEVEL CELL FLASH DESIGN
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Patent #:
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Issue Dt:
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09/02/2003
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Application #:
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09794480
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Filing Dt:
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02/26/2001
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Title:
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ASCENDING STAIRCASE READ TECHNIQUE FOR A MULTILEVEL CELL NAND FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09794482
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Filing Dt:
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02/26/2001
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Title:
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STAIRCASE PROGRAM VERIFY FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
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Patent #:
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Issue Dt:
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10/23/2001
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Application #:
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09794485
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Filing Dt:
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02/26/2001
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Title:
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Descending staircase read technique for a multilevel cell NAND flash memory device
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09803400
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Filing Dt:
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03/12/2001
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Publication #:
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Pub Dt:
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09/12/2002
| | | | |
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Title:
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HIGH VOLTAGE OXIDATION METHOD FOR HIGHLY RELIABLE FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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04/23/2002
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Application #:
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09817628
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Filing Dt:
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03/26/2001
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Title:
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FORMATION OF NON-VOLATILE MEMORY DEVICE COMPRISED OF AN ARRAY OF VERTICAL FIELD EFFECT TRANSISTOR STRUCTURES
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Patent #:
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Issue Dt:
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11/15/2005
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Application #:
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09836065
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Filing Dt:
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04/16/2001
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Publication #:
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Pub Dt:
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10/17/2002
| | | | |
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Title:
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SYSTEM AND METHOD FOR ERASE TEST OF INTEGRATED CIRCUIT DEVICE HAVING NON-HOMOGENEOUSLY SIZED SECTORS
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09842288
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Filing Dt:
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04/25/2001
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Title:
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ACCURATE VERIFY APPARATUS AND METHOD FOR NOR FLASH MEMORY CELLS IN THE PRESENCE OF HIGH COLUMN LEAKAGE
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Patent #:
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Issue Dt:
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02/04/2003
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Application #:
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09844692
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Filing Dt:
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04/27/2001
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Publication #:
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Pub Dt:
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10/31/2002
| | | | |
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Title:
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METHOD AND SYSTEM FOR REDUCING THINNING OF FIELD ISOLATION STRUCTURES IN A FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09851773
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Filing Dt:
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05/09/2001
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Title:
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THRESHOLD VOLTAGE COMPACTING FOR NON-VOLATILE SEMICONDUCTOR MEMORY DESIGNS
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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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09875056
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Filing Dt:
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06/05/2001
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Title:
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METHOD AND SYSTEM FOR QUALIFYING AN ONO LAYER IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09875073
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Filing Dt:
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06/05/2001
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Title:
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METHOD AND SYSTEM FOR QUALIFYING AN ONO LAYER IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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09904089
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Filing Dt:
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07/12/2001
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Title:
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OXIDE/NITRIDE OR OXIDE/NITRIDE/OXIDE THICKNESS MEASUREMENT USING SCATTEROMETRY
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09966702
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Filing Dt:
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09/28/2001
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Title:
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NITRIDE BARRIER LAYER FOR PROTECTION OF ONO STRUCTURE FROM TOP OXIDE LOSS IN A FABRICATION OF SONOS FLASH MEMORY
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Patent #:
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Issue Dt:
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02/21/2006
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Application #:
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10015033
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Filing Dt:
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12/11/2001
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Title:
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SWITCHED-CAPACITOR CONTROLLER TO CONTROL THE RISE TIMES OF ON-CHIP GENERATED HIGH VOLTAGES
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Patent #:
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Issue Dt:
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05/04/2004
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Application #:
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10091767
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Filing Dt:
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03/07/2002
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Title:
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PASSWORD AND DYNAMIC PROTECTION OF FLASH MEMORY DATA
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|
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Patent #:
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Issue Dt:
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01/20/2004
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Application #:
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10158044
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Filing Dt:
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05/30/2002
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Title:
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NITRIDE BARRIER LAYER FOR PROTECTION OF ONO STRUCTURE FROM TOP OXIDE LOSS IN FABRICATION OF SONOS FLASH MEMORY
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Patent #:
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Issue Dt:
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09/30/2003
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Application #:
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10244129
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Filing Dt:
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09/13/2002
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Title:
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A VOID-FREE INTERLAYER DIELECTRIC (ILD0) FOR 0.18-MICRON FLASH MEMORY SEMICONDUCTOR DEVICE
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