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Total properties:
35
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Patent #:
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Issue Dt:
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07/22/1997
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Application #:
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08551422
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Filing Dt:
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11/01/1995
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Title:
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TEMPERATURE COMPENSATED REFERENCE FOR OVERERASE CORRECTION CIRCUITRY IN A FLASH MEMORY
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Patent #:
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Issue Dt:
|
10/06/1998
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Application #:
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08610688
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Filing Dt:
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03/04/1996
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Title:
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E2PROM DEVICE HAVING ERASE GATE IN OXIDE ISOLATION REGION IN SHALLOW TRENCH AND METHOD OF MANUFACTURE THEREOF
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|
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Patent #:
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Issue Dt:
|
02/09/1999
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Application #:
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08653211
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Filing Dt:
|
05/24/1996
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Title:
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METHOD OF SCREENING MEMORY CELLS AT ROOM TEMPERATURE THAT WOULD BE REJECTED DURING HOT TEMPERATURE PROGRAMMING TESTS
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Patent #:
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Issue Dt:
|
05/12/1998
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Application #:
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08655357
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Filing Dt:
|
05/24/1996
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Title:
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METHOD OF SCREENING HOT TEMPERATURE ERASE REJECTS AT ROOM TEMPERATURE
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Patent #:
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Issue Dt:
|
12/29/1998
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Application #:
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08658038
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Filing Dt:
|
06/04/1996
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Title:
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METHOD AND SYSTEM FOR PROVIDING A DOUBLE DIFFUSE IMPLANT JUNCTION IN A FLASH DEVICE
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|
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Patent #:
|
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Issue Dt:
|
08/11/1998
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Application #:
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08668632
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Filing Dt:
|
06/18/1996
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Title:
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USING FLOATING GATE DEVICES AS SELECT GATE DEVICES FOR NAND FLASH MEMORY AND ITS BIAS SCHEME
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|
|
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Patent #:
|
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Issue Dt:
|
02/03/1998
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Application #:
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08686641
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Filing Dt:
|
07/24/1996
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Title:
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BIAS SCHEME OF PROGRAM INHIBIT FOR RANDOM PROGRAMMING IN A NAND FLASH MEMORY
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|
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Patent #:
|
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Issue Dt:
|
10/07/1997
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Application #:
|
08701288
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Filing Dt:
|
08/22/1996
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Title:
|
ERASE METHOD FOR PAGE MODE MULTIPLE BITS-PER-CELL FLASH EEPROM
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|
|
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Patent #:
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|
Issue Dt:
|
08/17/1999
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Application #:
|
08708428
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Filing Dt:
|
09/05/1996
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Title:
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AN IMPROVED ULTRATHIN OXYNITRIDE STRUCTURE AND PROCESS FOR VLSI APPLICTIONS
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|
|
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Patent #:
|
|
Issue Dt:
|
08/11/1998
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Application #:
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08723558
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Filing Dt:
|
09/30/1996
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Title:
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SYSTEM FOR PROVIDING TIGHT PROGRAM/ERASE SPEEDS THAT ARE INSENSITIVE TO PROCESS VARIATIONS
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|
|
|
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Patent #:
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|
Issue Dt:
|
05/05/1998
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Application #:
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08744962
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Filing Dt:
|
11/07/1996
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|
Title:
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DEVICE INCLUDING MEANS FOR PREVENTING TUNGSTEN SILICIDE LIFTING, AND METHOD OF FABRICATION THEREOF
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|
|
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Patent #:
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|
Issue Dt:
|
08/18/1998
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Application #:
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08799236
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Filing Dt:
|
02/14/1997
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|
Title:
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METHOD FOR ANNEALING DAMAGED SEMICONDUCTOR REGIONS ALLOWING FOR ENHANCED OXIDE GROWTH
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|
|
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Patent #:
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|
Issue Dt:
|
12/22/1998
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Application #:
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08801305
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Filing Dt:
|
02/18/1997
|
|
Title:
|
NON-VOLATILE STORAGE DEVICE REFRESH TIME DETECTOR
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|
|
|
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Patent #:
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|
Issue Dt:
|
09/08/1998
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Application #:
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08810164
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Filing Dt:
|
02/28/1997
|
|
Title:
|
CHANNEL HOT-CARRIER PAGE WRITE FOR NAND APPLICATIONS
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|
|
|
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Patent #:
|
|
Issue Dt:
|
09/29/1998
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Application #:
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08810170
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Filing Dt:
|
02/28/1997
|
|
Title:
|
OPTIMIZED BIASING SCHEME FOR NAND READ AND HOT-CARRIER WRITE OPERATIONS
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|
|
|
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Patent #:
|
|
Issue Dt:
|
08/03/1999
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Application #:
|
08813562
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Filing Dt:
|
03/07/1997
|
|
Title:
|
METHOD OF SPACER FORMATION AND SOURCE PROTECTION AFTER SELF- ALIGNED SOURCE IS FORMED AND DEVICE PROVIDED BY SUCH A METHOD
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/1999
|
Application #:
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08831571
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Filing Dt:
|
04/09/1997
|
|
Title:
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MEMORY CELL PROGRAMMING WITH CONTROLLED CURRENT INJECTION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/1999
|
Application #:
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08837556
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Filing Dt:
|
04/21/1997
|
|
Title:
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MULTILAYER FLOATING GATE FIELD EFFECT TRANSISTOR STRUCTURE FOR USE IN INTEGRATED CIRCUIT DEVICES
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|
|
|
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Patent #:
|
|
Issue Dt:
|
08/04/1998
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Application #:
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08853185
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Filing Dt:
|
05/09/1997
|
|
Title:
|
MULTIPLE BITS- PER- CELL FLASH EEPROM MEMORY CELLS WITH WIDE PROGRAM AND ERASE VT WINDOW
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/18/1998
|
Application #:
|
08858589
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Filing Dt:
|
05/19/1997
|
|
Title:
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MEMORY DEVICE USING A REDUCED WORD LINE VOLTAGE DURING READ OPERATIONS AND A METHOD OF ACCESSING SUCH A MEMORY DEVICE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/1999
|
Application #:
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08870045
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Filing Dt:
|
06/05/1997
|
|
Title:
|
TUBE FOR FLASH MINIATURE CARD
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2001
|
Application #:
|
08885140
|
Filing Dt:
|
06/30/1997
|
|
Title:
|
METHOD AND APPARATUS FOR CONTROLLING THE THICKNESS OF A GATE OXIDE IN A SEMICONDUCTOR MANUFACTURING PROCESS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/1999
|
Application #:
|
08891422
|
Filing Dt:
|
07/09/1997
|
|
Title:
|
METHOD OF MAKING A SEMICONDUCTOR DEVICE WITH ADJUSTABLE THRESHOLD VOLTAGE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/1998
|
Application #:
|
08914543
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Filing Dt:
|
08/19/1997
|
|
Title:
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HIGH VOLTAGE NMOS PASS GATE HAVING SUPPLY RANGE, AREA, AND SPEED ADVANTAGES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/1999
|
Application #:
|
08947123
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Filing Dt:
|
10/08/1997
|
|
Title:
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MEMORY CELL FOR STORING AT LEAST THREE LOGIC STATES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/1999
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Application #:
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08991466
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Filing Dt:
|
12/16/1997
|
|
Title:
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PROGRAMMING OF MEMORY CELLS USING CONNECTED FLOATING GATE ANALOG REFERENCE CELL
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2001
|
Application #:
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08993062
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Filing Dt:
|
12/18/1997
|
|
Title:
|
DEVICE INITIALIZING SYSTEM WITH PROGRAMMABLE ARRAY LOGIC CONFIGURED TO CAUSE NON-VOLATILE MEMORY TO OUTPUT ADDRESS AND DATA INFORMATION TO THE DEVICE IN A PRESCRIBED SEQUENCE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2002
|
Application #:
|
09008162
|
Filing Dt:
|
01/16/1998
|
|
Title:
|
FLASH MEMORY ARRAY WITH DUAL FUNCTION CONTROL LINES AND ASYMMETRICAL SOURCE AND DRAIN JUNCTIONS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2001
|
Application #:
|
09033642
|
Filing Dt:
|
03/03/1998
|
|
Title:
|
METHOD AND APPARATUS FOR CONTROLLING THE THICKNESS OF A GATE OXIDE IN A SEMICONDUCTOR MANUFACTURING PROCESS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/1999
|
Application #:
|
09127991
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Filing Dt:
|
08/03/1998
|
|
Title:
|
HIGH VOLTAGE NMOS PASS GATE HAVING SUPPLY RANGE, AREA, AND SPEED ADVANTAGES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2001
|
Application #:
|
09252854
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Filing Dt:
|
09/08/1998
|
|
Title:
|
NOVEL PROCESS FOR RELIABLE ULTRATHIN OXYNITRIDE FORMATION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2002
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Application #:
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09307312
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Filing Dt:
|
05/07/1999
|
|
Publication #:
|
|
Pub Dt:
|
02/07/2002
| | | | |
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Title:
|
METHOD AND APPARATUS FOR A SEMICONDUCTOR DEVICE WITH ADJUSTABLE THRESHOLD VOLTAGE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2000
|
Application #:
|
09336057
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Filing Dt:
|
06/18/1999
|
|
Title:
|
METHOD OF SPACER FORMATION AND SOURCE PROTECTION AFTER SELF-ALIGNED SOURCE FORMED AND A DEVICE PROVIDED BY SUCH A METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2001
|
Application #:
|
09461376
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Filing Dt:
|
12/15/1999
|
|
Title:
|
BIASING METHOD AND STRUCTURE FOR REDUCING BAND-TO-BAND AND/OR AVALANCHE CURRENTS DURING THE ERASE OF FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2004
|
Application #:
|
10233906
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Filing Dt:
|
09/03/2002
|
|
Title:
|
FLASH MEMORY ARRAY WITH DUAL FUNCTION CONTROL LINES AND ASYMMETRICAL SOURCE AND DRAIN JUNCTIONS
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|
