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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:019069/0040   Pages: 6
Recorded: 03/27/2007
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 35
1
Patent #:
6017786
Issue Dt:
01/25/2000
Application #:
08982186
Filing Dt:
12/17/1997
Title:
METHOD FOR FORMING A LOW BARRIER HEIGHT OXIDE LAYER ON A SILICON SUBSTRATE
2
Patent #:
6001688
Issue Dt:
12/14/1999
Application #:
08986860
Filing Dt:
12/08/1997
Title:
METHOD OF ELIMINATING POLY STRINGER IN A MEMORY DEVICE
3
Patent #:
6046085
Issue Dt:
04/04/2000
Application #:
08986951
Filing Dt:
12/08/1997
Title:
ELIMINATION OF POLY STRINGERS WITH STRAIGHT POLY PROFILE
4
Patent #:
5933729
Issue Dt:
08/03/1999
Application #:
08986953
Filing Dt:
12/08/1997
Title:
REDUCTION OF ONO FENCE DURING SELF-ALIGNED ETCH TO ELIMINATE POLY STRINGERS
5
Patent #:
5994780
Issue Dt:
11/30/1999
Application #:
08991052
Filing Dt:
12/16/1997
Title:
SEMICONDUCTOR DEVICE WITH MULTIPLE CONTACT SIZES
6
Patent #:
6072191
Issue Dt:
06/06/2000
Application #:
08991299
Filing Dt:
12/16/1997
Title:
INTERLEVEL DIELECTRIC THICKNESS MONITOR FOR COMPLEX SEMICONDUCTOR CHIPS
7
Patent #:
5973353
Issue Dt:
10/26/1999
Application #:
08992951
Filing Dt:
12/18/1997
Title:
METHODS AND ARRANGEMENTS FOR FORMING A TAPERED FLOATING GATE IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
8
Patent #:
6667511
Issue Dt:
12/23/2003
Application #:
08993368
Filing Dt:
12/18/1997
Title:
NOVEL NAND TYPE CORE CELL STRUCTURE FOR A HIGH DENSITY FLASH MEMORY DEVICE HAVING A UNIQUE SELECT GATE TRANSISTOR CONFIGURATION
9
Patent #:
6166439
Issue Dt:
12/26/2000
Application #:
09000739
Filing Dt:
12/30/1997
Title:
A LOW DIELECTRIC CONSTANT MATERIAL AND METHOD OF APPLICATION TO ISOLATE CONDUCTIVE LINES
10
Patent #:
5972749
Issue Dt:
10/26/1999
Application #:
09002783
Filing Dt:
01/05/1998
Title:
METHOD FOR PREVENTING P1 PUNCHTHROUGH
11
Patent #:
6211074
Issue Dt:
04/03/2001
Application #:
09076584
Filing Dt:
05/12/1998
Title:
METHODS AND ARRANGEMENTS FOR REDUCING STRESS AND PREVENTING CRACKING IN A SILICIDE LAYER
12
Patent #:
6159794
Issue Dt:
12/12/2000
Application #:
09076662
Filing Dt:
05/12/1998
Title:
METHODS FOR REMOVING SILICIDE RESIDUE IN A SEMICONDUCTOR DEVICE
13
Patent #:
6074956
Issue Dt:
06/13/2000
Application #:
09076663
Filing Dt:
05/12/1998
Title:
METHODS FOR PREVENTING SILICIDE RESIDUE FORMATION IN A SEMICONDUCTOR DEVICE
14
Patent #:
5948703
Issue Dt:
09/07/1999
Application #:
09092924
Filing Dt:
06/08/1998
Title:
METHOD OF SOFT-LANDING GATE ETCHING TO PREVENT GATE OXIDE DAMAGE
15
Patent #:
6159860
Issue Dt:
12/12/2000
Application #:
09118375
Filing Dt:
07/17/1998
Title:
METHOD FOR ETCHING LAYERS ON A SEMICONDUCTOR WAFER IN A SINGLE ETCHING CHAMBER
16
Patent #:
5977601
Issue Dt:
11/02/1999
Application #:
09118377
Filing Dt:
07/17/1998
Title:
METHOD FOR ETCHING MEMORY GATE STACK USING THIN RESIST LAYER
17
Patent #:
6110779
Issue Dt:
08/29/2000
Application #:
09118382
Filing Dt:
07/17/1998
Title:
METHOD AND STRUCTURE OF ETCHING A MEMORY CELL POLISILICON GATE LAYER USING RESIST MASK AND ETCHED SILICON OXYNITRIDE
18
Patent #:
6124640
Issue Dt:
09/26/2000
Application #:
09144506
Filing Dt:
08/31/1998
Title:
SCALABLE AND RELIABLE INTEGRATED CIRCUIT INTER-LEVEL DIELECTRIC
19
Patent #:
6133619
Issue Dt:
10/17/2000
Application #:
09144521
Filing Dt:
08/31/1998
Title:
REDUCTION OF SILICON OXYNITRIDE FILM DELAMINATION IN INTEGRATED CIRCUIT INTER-LEVEL DIELECTRICS
20
Patent #:
6060741
Issue Dt:
05/09/2000
Application #:
09154072
Filing Dt:
09/16/1998
Title:
STACKED GATE STRUCTURE FOR FLASH MEMORY APPLICATION
21
Patent #:
6011289
Issue Dt:
01/04/2000
Application #:
09154073
Filing Dt:
09/16/1998
Title:
METAL OXIDE STACK FOR FLASH MEMORY APPLICATION
22
Patent #:
6080639
Issue Dt:
06/27/2000
Application #:
09199265
Filing Dt:
11/25/1998
Title:
SEMICONDUCTOR DEVICE CONTAINING P-HDP INTERDIELECTRIC LAYER
23
Patent #:
6515328
Issue Dt:
02/04/2003
Application #:
09244429
Filing Dt:
02/04/1999
Title:
SEMICONDUCTOR DEVICES WITH REDUCED CONTROL GATE DIMENSIONS
24
Patent #:
6066873
Issue Dt:
05/23/2000
Application #:
09271330
Filing Dt:
03/18/1999
Title:
METHOD AND APPARATUS FOR PREVENTING P1 PUNCHTHROUGH
25
Patent #:
6372651
Issue Dt:
04/16/2002
Application #:
09286464
Filing Dt:
04/06/1999
Title:
METHOD FOR TRIMMING A PHOTORESIST PATTERN LINE FOR MEMORY GATE ETCHING
26
Patent #:
6232630
Issue Dt:
05/15/2001
Application #:
09348583
Filing Dt:
07/07/1999
Title:
LIGHT FLOATING GATE DOPING TO IMPROVE TUNNEL OXIDE RELIABILITY
27
Patent #:
6235586
Issue Dt:
05/22/2001
Application #:
09352801
Filing Dt:
07/13/1999
Title:
THIN FLOATING GATE AND CONDUCTIVE SELECT GATE IN SITU DOPED AMORPHOUS SILICON MATERIAL FOR NAND TYPE FLASH MEMORY DEVICE APPLICATIONS
28
Patent #:
6211058
Issue Dt:
04/03/2001
Application #:
09353781
Filing Dt:
07/15/1999
Title:
SEMICONDUCTOR DEVICE WITH MULTIPLE CONTACT SIZES
29
Patent #:
6433383
Issue Dt:
08/13/2002
Application #:
09357333
Filing Dt:
07/20/1999
Title:
METHODS AND ARRANGEMENTS FOR FORMING A SINGLE INTERPOLY DIELECTRIC LAYER IN A SEMICONDUCTOR DEVICE
30
Patent #:
6383939
Issue Dt:
05/07/2002
Application #:
09375504
Filing Dt:
08/17/1999
Title:
METHOD FOR ETCHING MEMORY GATE STACK USING THIN RESIST LAYER
31
Patent #:
6316293
Issue Dt:
11/13/2001
Application #:
09531749
Filing Dt:
03/20/2000
Title:
A METHOD OF FORMING A NAND -TYPE FLASH MEMORY DEVICE H AVING A NON-STACKED SELECT GATE TRANSISTOR STRUCTURE
32
Patent #:
6534411
Issue Dt:
03/18/2003
Application #:
09548616
Filing Dt:
04/13/2000
Title:
METHOD OF HIGH DENSITY PLASMA METAL ETCHING
33
Patent #:
6350627
Issue Dt:
02/26/2002
Application #:
09548741
Filing Dt:
04/13/2000
Title:
Interlevel dielectric thickness monitor for complex semiconductor chips
34
Patent #:
6452225
Issue Dt:
09/17/2002
Application #:
09617820
Filing Dt:
07/17/2000
Title:
Method and structure of etching a memory cell polysilicon gate layer using resist mask and etched silicon oxynitride
35
Patent #:
6436850
Issue Dt:
08/20/2002
Application #:
09652132
Filing Dt:
08/31/2000
Title:
METHOD OF DEGASSING LOW K DIELECTRIC FOR METAL DEPOSITION
Assignor
1
SPANSION INC.
Exec Dt:
01/31/2007
Assignee
1
SPANSION LLC
915 DEGUIGNE DRIVE, P.O. BOX 3453
MAIL STOP 250
SUNNYVALE, CALIFORNIA 94088-3453
Correspondence name and address
RAYMOND E. FRITZ
915 DEGUIGNE DRIVE, P.O. BOX 3453
MAIL STOP 250
SUNNYVALE, CA 94088-3453

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