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Patent Assignment Details
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Reel/Frame:019069/0119   Pages: 6
Recorded: 03/27/2007
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 35
1
Patent #:
6188606
Issue Dt:
02/13/2001
Application #:
09369600
Filing Dt:
08/06/1999
Title:
MULTI STATE SENSING OF NAND MEMORY CELLS BY VARYING SOURCE BIAS
2
Patent #:
6218689
Issue Dt:
04/17/2001
Application #:
09369638
Filing Dt:
08/06/1999
Title:
METHOD FOR PROVIDING A DOPANT LEVEL FOR POLYSILICON FOR FLASH MEMORY DEVICES
3
Patent #:
6166951
Issue Dt:
12/26/2000
Application #:
09370010
Filing Dt:
08/06/1999
Title:
MULTI STATE SENSING OF NAND MEMORY CELLS BY APPLYING REVERSE-BIAS VOLTAGE
4
Patent #:
6580639
Issue Dt:
06/17/2003
Application #:
09372406
Filing Dt:
08/10/1999
Title:
METHOD OF REDUCING PROGRAM DISTURBS IN NAND TYPE FLASH MEMORY DEVICES
5
Patent #:
6153470
Issue Dt:
11/28/2000
Application #:
09374059
Filing Dt:
08/12/1999
Title:
FLOATING GATE ENGINEERING TO IMPROVE TUNNEL OXIDE RELIABILITY FOR FLASH MEMORY DEVICES
6
Patent #:
6141244
Issue Dt:
10/31/2000
Application #:
09388696
Filing Dt:
09/02/1999
Title:
MULTI LEVEL SENSING OF NAND MEMORY CELLS BY EXTERNAL BIAS CURRENT
7
Patent #:
6177316
Issue Dt:
01/23/2001
Application #:
09412278
Filing Dt:
10/05/1999
Title:
POST BARRIER METAL CONTACT IMPLANTATION TO MINIMIZE OUT DIFFUSION FOR NAND DEVICE
8
Patent #:
6181605
Issue Dt:
01/30/2001
Application #:
09414750
Filing Dt:
10/06/1999
Title:
GLOBAL ERASE/PROGRAM VERIFICATION APPARATUS AND METHOD
9
Patent #:
6291296
Issue Dt:
09/18/2001
Application #:
09416382
Filing Dt:
10/12/1999
Title:
METHOD FOR REMOVING ANTI-REFLECTIVE COATING LAYER USING PLASMA ETCH PROCESS BEFORE CONTACT CMP
10
Patent #:
6136649
Issue Dt:
10/24/2000
Application #:
09416389
Filing Dt:
10/12/1999
Title:
METHOD FOR REMOVING ANTI-REFLECTIVE COATING LAYER USING PLASMA ETCH PROCESS AFTER CONTACT CMP
11
Patent #:
6185130
Issue Dt:
02/06/2001
Application #:
09420209
Filing Dt:
10/18/1999
Title:
PROGRAMMABLE CURRENT SOURCE
12
Patent #:
6327183
Issue Dt:
12/04/2001
Application #:
09480868
Filing Dt:
01/10/2000
Title:
NONLINEAR STEPPED PROGRAMMING VOLTAGE
13
Patent #:
6812521
Issue Dt:
11/02/2004
Application #:
09492243
Filing Dt:
01/27/2000
Title:
METHOD AND APPARATUS FOR IMPROVED PERFORMANCE OF FLASH MEMORY CELL DEVICES
14
Patent #:
6269025
Issue Dt:
07/31/2001
Application #:
09500699
Filing Dt:
02/09/2000
Title:
Memory system having a program and erase voltage modifier
15
Patent #:
6420752
Issue Dt:
07/16/2002
Application #:
09502163
Filing Dt:
02/11/2000
Title:
SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACTS USING A LINER OXIDE LAYER
16
Patent #:
6246610
Issue Dt:
06/12/2001
Application #:
09511652
Filing Dt:
02/22/2000
Title:
Symmetrical program and erase scheme to improve erase time degradation in NAND devices
17
Patent #:
6304487
Issue Dt:
10/16/2001
Application #:
09514404
Filing Dt:
02/28/2000
Title:
Register driven means to control programming voltages
18
Patent #:
6246611
Issue Dt:
06/12/2001
Application #:
09514560
Filing Dt:
02/28/2000
Title:
System for erasing a memory cell
19
Patent #:
6295228
Issue Dt:
09/25/2001
Application #:
09514933
Filing Dt:
02/28/2000
Title:
System for programming memory cells
20
Patent #:
6351017
Issue Dt:
02/26/2002
Application #:
09533057
Filing Dt:
03/22/2000
Title:
High voltage transistor with modified field implant mask
21
Patent #:
6445051
Issue Dt:
09/03/2002
Application #:
09563797
Filing Dt:
05/02/2000
Title:
METHOD AND SYSTEM FOR PROVIDING CONTACTS WITH GREATER TOLERANCE FOR MISALIGNMENT IN A FLASH MEMORY
22
Patent #:
6348406
Issue Dt:
02/19/2002
Application #:
09586264
Filing Dt:
05/31/2000
Title:
Method for using a low dielectric constant layer as a semiconductor anti-reflective coating
23
Patent #:
6376389
Issue Dt:
04/23/2002
Application #:
09588117
Filing Dt:
05/31/2000
Title:
METHOD FOR ELIMINATING ANTI-REFLECTIVE COATING IN SEMICONDUCTORS
24
Patent #:
6529410
Issue Dt:
03/04/2003
Application #:
09665916
Filing Dt:
09/20/2000
Title:
NAND ARRAY STRUCTURE AND METHOD WITH BURIED LAYER
25
Patent #:
6271087
Issue Dt:
08/07/2001
Application #:
09685968
Filing Dt:
10/10/2000
Title:
Method for forming self-aligned contacts and local interconnects using self-aligned local interconnects
26
Patent #:
6482699
Issue Dt:
11/19/2002
Application #:
09685972
Filing Dt:
10/10/2000
Title:
METHOD FOR FORMING SELF-ALIGNED CONTACTS AND LOCAL INTERCONNECTS USING DECOUPLED LOCAL INTERCONNECT PROCESS
27
Patent #:
6545912
Issue Dt:
04/08/2003
Application #:
09727656
Filing Dt:
11/30/2000
Title:
ERASE VERIFY MODE TO EVALUATE NEGATIVE VT'S
28
Patent #:
6727195
Issue Dt:
04/27/2004
Application #:
09777457
Filing Dt:
02/06/2001
Publication #:
US20010045648
Pub Dt:
11/29/2001
Title:
METHOD AND SYSTEM FOR DECREASING THE SPACES BETWEEN WORDLINES
29
Patent #:
6306713
Issue Dt:
10/23/2001
Application #:
09799469
Filing Dt:
03/05/2001
Title:
Method for forming self-aligned contacts and local interconnects for salicided gates using a secondary spacer
30
Patent #:
6509229
Issue Dt:
01/21/2003
Application #:
09850484
Filing Dt:
05/07/2001
Title:
METHOD FOR FORMING SELF-ALIGNED CONTACTS USING CONSUMABLE SPACERS
31
Patent #:
6933554
Issue Dt:
08/23/2005
Application #:
09904042
Filing Dt:
07/11/2001
Title:
RECESSED TUNNEL OXIDE PROFILE FOR IMPROVED RELIABILITY IN NAND DEVICES
32
Patent #:
6504757
Issue Dt:
01/07/2003
Application #:
09922415
Filing Dt:
08/03/2001
Title:
DOUBLE BOOSTING SCHEME FOR NAND TO IMPROVE PROGRAM INHIBIT CHARACTERISTICS
33
Patent #:
6525966
Issue Dt:
02/25/2003
Application #:
10010985
Filing Dt:
12/05/2001
Title:
METHOD AND APPARATUS FOR ADJUSTING ON-CHIP CURRENT REFERENCE FOR EEPROM SENSING
34
Patent #:
6514830
Issue Dt:
02/04/2003
Application #:
10044510
Filing Dt:
01/11/2002
Title:
METHOD OF MANUFACTURING HIGH VOLTAGE TRANSISTOR WITH MODIFIED FIELD IMPLANT MASK
35
Patent #:
6475847
Issue Dt:
11/05/2002
Application #:
10109526
Filing Dt:
03/27/2002
Title:
METHOD FOR FORMING A SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACTS USING A LINER OXIDE LAYER
Assignor
1
SPANSION INC.
Exec Dt:
01/31/2007
Assignee
1
SPANSION LLC
915 DEGUIGNE DRIVE, P.O. BOX 3453
MAIL STOP 250
SUNNYVALE, CALIFORNIA 94088-3453
Correspondence name and address
RAYMOND E. FRITZ
915 DEGUIGNE DRIVE, P.O. BOX 3453
MAIL STOP 250
SUNNYVALE, CA 94088-3453

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