Total properties:
35
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Patent #:
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Issue Dt:
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09/04/2001
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Application #:
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09609468
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Filing Dt:
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07/03/2000
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Title:
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Species implantation for minimizing interface defect density in flash memory devices
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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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09609793
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Filing Dt:
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07/03/2000
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Title:
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AUTOMATED DETERMINATION AND DISPLAY OF THE PHYSICAL LOCATION OF A FAILED CELL IN AN ARRAY OF MEMORY CELLS
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Patent #:
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Issue Dt:
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06/11/2002
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Application #:
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09627664
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Filing Dt:
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07/28/2000
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Title:
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Nitrogen implant after bit-line formation for ono flash memory devices
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Patent #:
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Issue Dt:
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06/18/2002
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Application #:
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09654831
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Filing Dt:
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09/01/2000
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Title:
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ARRANGEMENT FOR PROGRAMMING SELECTED DEVICE REGISTERS DURING INITIALIZATION FROM AN EXTERNAL MEMORY
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Patent #:
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Issue Dt:
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06/26/2001
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Application #:
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09692881
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Filing Dt:
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10/23/2000
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Title:
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Automatic program disturb with intelligent soft programming for flash cells
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Patent #:
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Issue Dt:
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03/26/2002
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Application #:
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09694688
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Filing Dt:
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10/23/2000
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Title:
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Low column leakage NOR flash array - single cell implementation
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Patent #:
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Issue Dt:
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02/25/2003
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Application #:
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09699972
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Filing Dt:
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10/30/2000
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Title:
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SOURCE SIDE BORON IMPLANTING AND DIFFUSING DEVICE ARCHITECTURE FOR DEEP SUB 0.18 MICRON FLASH MEMORY
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Patent #:
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Issue Dt:
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12/18/2001
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Application #:
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09717550
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Filing Dt:
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11/21/2000
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Title:
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Method and system for embedded chip erase verification
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Patent #:
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Issue Dt:
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07/22/2003
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Application #:
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09739733
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Filing Dt:
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12/18/2000
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Title:
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METHODS TO FORM REDUCED DIMENSION BIT-LINE ISOLATION IN THE MANUFACTURE OF NON-VOLATILE MEMORY DEVICES
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Patent #:
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Issue Dt:
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02/05/2002
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Application #:
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09795849
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Filing Dt:
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02/28/2001
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Title:
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Data retention characteristics as a result of high temperature bake
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09795854
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Filing Dt:
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02/28/2001
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Title:
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TAILORED ERASE METHOD USING HIGHER PROGRAM VT AND HIGHER NEGATIVE GATE ERASE
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Patent #:
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Issue Dt:
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10/23/2001
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Application #:
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09795856
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Filing Dt:
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02/28/2001
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Title:
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Negative gate erase
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Patent #:
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Issue Dt:
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12/10/2002
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Application #:
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09795865
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Filing Dt:
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02/28/2001
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Title:
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SINGLE BIT ARRAY EDGES
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Patent #:
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Issue Dt:
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09/24/2002
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Application #:
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09796282
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Filing Dt:
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02/28/2001
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Publication #:
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Pub Dt:
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10/31/2002
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Title:
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HIGHER PROGRAM VT AND FASTER PROGRAMMING RATES BASED ON IMPROVED ERASE METHODS
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09824166
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Filing Dt:
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04/02/2001
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Title:
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SYSTEM AND METHOD TO FACILITATE STABILIZATION OF REFERENCE VOLTAGE SIGNALS IN MEMORY DEVICES
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Patent #:
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|
Issue Dt:
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02/04/2003
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Application #:
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09873643
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Filing Dt:
|
06/04/2001
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Title:
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METHOD AND APPARATUS FOR BOOSTING BITLINES FOR LOW VCC READ
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Patent #:
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|
Issue Dt:
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08/20/2002
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Application #:
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09879738
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Filing Dt:
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06/12/2001
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Title:
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NOVEL RE-OXIDATION APPROACH TO IMPROVE PERIPHERAL GATE OXIDE INTEGRITY IN A TUNNEL NITRIDE OXIDATION PROCESS
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Patent #:
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|
Issue Dt:
|
06/04/2002
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Application #:
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09882242
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Filing Dt:
|
06/15/2001
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Title:
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SPECIES IMPLANTATION FOR MINIMIZING INTERFACE DEFECT DENSITY IN FLASH MEMORY DEVICES
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|
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Patent #:
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|
Issue Dt:
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09/10/2002
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Application #:
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09884565
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Filing Dt:
|
06/19/2001
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Title:
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LOW COLUMN LEAKAGE NOR FLASH ARRAY-DOUBLE CELL IMPLEMENTATION
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Patent #:
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|
Issue Dt:
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10/15/2002
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Application #:
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09885490
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Filing Dt:
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06/20/2001
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Title:
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METHOD OF MANUFACTURING SPACER ETCH MASK FOR SILICON-OXIDE-NITRIDE-OXIDE-SILICON (SONOS) TYPE NONVOLATILE MEMORY
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Patent #:
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|
Issue Dt:
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01/28/2003
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Application #:
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09886861
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Filing Dt:
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06/21/2001
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Title:
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ERASE METHOD FOR DUAL BIT VIRTUAL GROUND FLASH
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Patent #:
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|
Issue Dt:
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05/31/2005
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Application #:
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09891885
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Filing Dt:
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06/26/2001
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Publication #:
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Pub Dt:
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12/26/2002
| | | | |
Title:
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ESD IMPLANT FOLLOWING SPACER DEPOSITION
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|
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Patent #:
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|
Issue Dt:
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07/23/2002
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Application #:
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09892189
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Filing Dt:
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06/26/2001
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Title:
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MODULATED CHARGE PUMP WHICH USES AN ANALOG TO DIGITAL CONVERTER TO COMPENSATE FOR SUPPLY VOLTAGE VARIATIONS
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Patent #:
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|
Issue Dt:
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11/11/2003
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Application #:
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09968456
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Filing Dt:
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10/01/2001
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Title:
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SALICIDED GATE FOR VIRTUAL GROUND ARRAYS
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Patent #:
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|
Issue Dt:
|
05/20/2003
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Application #:
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09968465
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Filing Dt:
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10/01/2001
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Publication #:
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|
Pub Dt:
|
05/08/2003
| | | | |
Title:
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SALICIDED GATE FOR VIRTUAL GROUND ARRAYS
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|
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Patent #:
|
|
Issue Dt:
|
10/07/2003
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Application #:
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09971483
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Filing Dt:
|
10/05/2001
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Title:
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METHOD OF FABRICATING DOUBLE DENSED CORE GATES IN SONOS FLASH MEMORY
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|
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Patent #:
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|
Issue Dt:
|
02/04/2003
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Application #:
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10050254
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Filing Dt:
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01/16/2002
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Title:
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NEGATIVE PUMP REGULATOR USING MOS CAPACITOR
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|
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Patent #:
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|
Issue Dt:
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03/04/2003
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Application #:
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10050257
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Filing Dt:
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01/16/2002
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Title:
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SOURCE SIDE SENSING SCHEME FOR VIRTUAL GROUND READ OF FLASH EPROM ARRAY WITH ADJACENT BIT PRECHARGE
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Patent #:
|
|
Issue Dt:
|
06/06/2006
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Application #:
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10050342
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Filing Dt:
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01/16/2002
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Title:
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METHOD AND APPARATUS FOR PRE-CHARGING NEGATIVE PUMP MOS REGULATION CAPACITORS
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|
|
Patent #:
|
|
Issue Dt:
|
08/03/2004
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Application #:
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10050394
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Filing Dt:
|
01/16/2002
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Title:
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DIODE FABRICATION FOR ESD/EOS PROTECTION
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|
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Patent #:
|
|
Issue Dt:
|
05/20/2003
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Application #:
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10050483
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Filing Dt:
|
01/16/2002
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Title:
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CHARGE INJECTION
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|
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Patent #:
|
|
Issue Dt:
|
03/11/2003
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Application #:
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10050650
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Filing Dt:
|
01/16/2002
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Title:
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METHOD AND APPARATUS FOR SOFT PROGRAM VERIFICATION IN A MEMORY DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
07/08/2003
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Application #:
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10173262
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Filing Dt:
|
06/17/2002
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Title:
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HIGHER PROGRAM VT AND FASTER PROGRAMMING RATES BASED ON IMPROVED ERASE METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2003
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Application #:
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10223486
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Filing Dt:
|
08/19/2002
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Title:
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SYSTEM AND METHOD TO FACILITATE STABILIZATION OF REFERENCE VOLTAGE SIGNALS IN MEMORY DEVICES
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|
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Patent #:
|
|
Issue Dt:
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07/27/2004
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Application #:
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10413829
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Filing Dt:
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04/15/2003
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Publication #:
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|
Pub Dt:
|
09/25/2003
| | | | |
Title:
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MEMORY DEVICE
|
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