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Patent Assignment Details
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Reel/Frame:019069/0336   Pages: 6
Recorded: 03/27/2007
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 35
1
Patent #:
6700201
Issue Dt:
03/02/2004
Application #:
10013902
Filing Dt:
12/11/2001
Title:
REDUCTION OF SECTOR CONNECTING LINE CAPACITANCE USING STAGGERED METAL LINES
2
Patent #:
6723605
Issue Dt:
04/20/2004
Application #:
10022292
Filing Dt:
12/15/2001
Title:
METHOD FOR MANUFACTURING MEMORY WITH HIGH CONDUCTIVITY BITLINE AND SHALLOW TRENCH ISOLATION INTEGRATION
3
Patent #:
6653190
Issue Dt:
11/25/2003
Application #:
10023436
Filing Dt:
12/15/2001
Title:
FLASH MEMORY WITH CONTROLLED WORDLINE WIDTH
4
Patent #:
6639271
Issue Dt:
10/28/2003
Application #:
10027253
Filing Dt:
12/20/2001
Title:
FULLY ISOLATED DIELECTRIC MEMORY CELL STRUCTURE FOR A DUAL BIT NITRIDE STORAGE DEVICE AND PROCESS FOR MAKING SAME
5
Patent #:
6566230
Issue Dt:
05/20/2003
Application #:
10032630
Filing Dt:
12/27/2001
Title:
SHALLOW TRENCH ISOLATION SPACER FOR WEFF IMPROVEMENT
6
Patent #:
6740926
Issue Dt:
05/25/2004
Application #:
10032646
Filing Dt:
12/27/2001
Title:
PLANAR TRANSISTOR STRUCTURE USING ISOLATION IMPLANTS FOR IMPROVED VSS RESISTANCE AND FOR PROCESS SIMPLIFICATION
7
Patent #:
6654285
Issue Dt:
11/25/2003
Application #:
10083789
Filing Dt:
02/27/2002
Title:
METHOD OF MATCHING CORE CELL AND REFERENCE CELL SOURCE RESISTANCES
8
Patent #:
6737703
Issue Dt:
05/18/2004
Application #:
10095512
Filing Dt:
03/12/2002
Title:
MEMORY ARRAY WITH BURIED BIT LINES
9
Patent #:
6642573
Issue Dt:
11/04/2003
Application #:
10097912
Filing Dt:
03/13/2002
Title:
USE OF HIGH-K DIELECTRIC MATERIAL IN MODIFIED ONO STRUCTURE FOR SEMICONDUCTOR DEVICES
10
Patent #:
6593590
Issue Dt:
07/15/2003
Application #:
10112976
Filing Dt:
03/28/2002
Title:
A TEST STRUCTURE APPARATUS FOR MEASURING STANDBY CURRENT IN FLASH MEMORY DEVICES
11
Patent #:
6750066
Issue Dt:
06/15/2004
Application #:
10117818
Filing Dt:
04/08/2002
Title:
PRECISION HIGH-K INTERGATE DIELECTRIC LAYER
12
Patent #:
6762454
Issue Dt:
07/13/2004
Application #:
10118363
Filing Dt:
04/08/2002
Title:
STACKED POLYSILICON LAYER FOR BORON PENETRATION INHIBITION
13
Patent #:
6806165
Issue Dt:
10/19/2004
Application #:
10120116
Filing Dt:
04/09/2002
Title:
ISOLATION TRENCH FILL PROCESS
14
Patent #:
6548855
Issue Dt:
04/15/2003
Application #:
10147622
Filing Dt:
05/16/2002
Title:
NON-VOLATILE MEMORY DIELECTRIC AS CHARGE PUMP DIELECTRIC
15
Patent #:
6610577
Issue Dt:
08/26/2003
Application #:
10150204
Filing Dt:
05/15/2002
Title:
SELF-ALIGNED POLYSILICON POLISH
16
Patent #:
6806155
Issue Dt:
10/19/2004
Application #:
10150255
Filing Dt:
05/15/2002
Title:
METHOD AND SYSTEM FOR SCALING NONVOLATILE MEMORY CELLS
17
Patent #:
6605517
Issue Dt:
08/12/2003
Application #:
10150282
Filing Dt:
05/15/2002
Title:
METHOD FOR MINIMIZING NITRIDE RESIDUE ON A SILICON WAFER
18
Patent #:
6596586
Issue Dt:
07/22/2003
Application #:
10152747
Filing Dt:
05/21/2002
Title:
METHOD OF FORMING LOW RESISTANCE COMMON SOURCE LINE FOR FLASH MEMORY DEVICES
19
Patent #:
6735123
Issue Dt:
05/11/2004
Application #:
10164895
Filing Dt:
06/07/2002
Title:
HIGH DENSITY DUAL BIT FLASH MEMORY CELL WITH NON PLANAR STRUCTURE
20
Patent #:
6811932
Issue Dt:
11/02/2004
Application #:
10165383
Filing Dt:
06/06/2002
Title:
METHOD AND SYSTEM FOR DETERMINING FLOW RATES FOR CONTACT FORMATION
21
Patent #:
6607925
Issue Dt:
08/19/2003
Application #:
10165837
Filing Dt:
06/06/2002
Title:
HARD MASK REMOVAL PROCESS INCLUDING ISOLATION DIELECTRIC REFILL
22
Patent #:
6670691
Issue Dt:
12/30/2003
Application #:
10174550
Filing Dt:
06/18/2002
Title:
SHALLOW TRENCH ISOLATION FILL PROCESS
23
Patent #:
6617639
Issue Dt:
09/09/2003
Application #:
10176594
Filing Dt:
06/21/2002
Title:
USE OF HIGH-K DIELECTRIC MATERIAL FOR ONO AND TUNNEL OXIDE TO IMPROVE FLOATING GATE FLASH MEMORY COUPLING
24
Patent #:
6627945
Issue Dt:
09/30/2003
Application #:
10189651
Filing Dt:
07/03/2002
Title:
MEMORY DEVICE AND METHOD OF MAKING
25
Patent #:
7052969
Issue Dt:
05/30/2006
Application #:
10190002
Filing Dt:
07/03/2002
Title:
METHOD FOR SEMICONDUCTOR WAFER PLANARIZATION BY ISOLATION MATERIAL GROWTH
26
Patent #:
6770523
Issue Dt:
08/03/2004
Application #:
10190397
Filing Dt:
07/02/2002
Title:
METHOD FOR SEMICONDUCTOR WAFER PLANARIZATION BY CMP STOP LAYER FORMATION
27
Patent #:
6753570
Issue Dt:
06/22/2004
Application #:
10223920
Filing Dt:
08/20/2002
Title:
MEMORY DEVICE AND METHOD OF MAKING
28
Patent #:
6754109
Issue Dt:
06/22/2004
Application #:
10282847
Filing Dt:
10/29/2002
Title:
METHOD OF PROGRAMMING IN-SERIES MEMORY CELLS
29
Patent #:
7015135
Issue Dt:
03/21/2006
Application #:
10316569
Filing Dt:
12/10/2002
Publication #:
US20040110368
Pub Dt:
06/10/2004
Title:
METHOD AND SYSTEM FOR REDUCING CONTACT DEFECTS USING NON CONVENTIONAL CONTACT FORMATION METHOD FOR SEMICONDUCTOR CELLS
30
Patent #:
6905971
Issue Dt:
06/14/2005
Application #:
10331938
Filing Dt:
12/30/2002
Title:
TREATMENT OF DIELECTRIC MATERIAL TO ENHANCE ETCH RATE
31
Patent #:
6953752
Issue Dt:
10/11/2005
Application #:
10358756
Filing Dt:
02/05/2003
Title:
REDUCED SILICON GOUGING AND COMMON SOURCE LINE RESISTANCE IN SEMICONDUCTOR DEVICES
32
Patent #:
6723638
Issue Dt:
04/20/2004
Application #:
10358866
Filing Dt:
02/05/2003
Title:
PERFORMANCE IN FLASH MEMORY DEVICES
33
Patent #:
6781885
Issue Dt:
08/24/2004
Application #:
10379885
Filing Dt:
03/05/2003
Title:
METHOD OF PROGRAMMING A MEMORY CELL
34
Patent #:
6861307
Issue Dt:
03/01/2005
Application #:
10631199
Filing Dt:
07/31/2003
Publication #:
US20040021172
Pub Dt:
02/05/2004
Title:
FULLY ISOLATED DIELECTRIC MEMORY CELL STRUCTURE FOR A DUAL BIT NITRIDE STORAGE DEVICE AND PROCESS FOR MAKING SAME
35
Patent #:
7001807
Issue Dt:
02/21/2006
Application #:
10997345
Filing Dt:
11/24/2004
Title:
FULLY ISOLATED DIELECTRIC MEMORY CELL STRUCTURE FOR A DUAL BIT NITRIDE STORAGE DEVICE AND PROCESS FOR MAKING SAME
Assignor
1
SPANSION INC.
Exec Dt:
01/31/2007
Assignee
1
SPANSION LLC
915 DEGUIGNE DRIVE, P.O. BOX 3453
MAIL STOP 250
SUNNYVALE, CALIFORNIA 94088-3453
Correspondence name and address
RAYMOND E. FRITZ
915 DEGUIGNE DRIVE, P.O. BOX 3453
MAIL STOP 250
SUNNYVALE, CA 94088-3453

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