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Patent Assignment Details
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Reel/Frame:019069/0372   Pages: 6
Recorded: 03/27/2007
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 25
1
Patent #:
Issue Dt:
09/28/2004
Application #:
10406415
Filing Dt:
04/03/2003
Publication #:
Pub Dt:
10/07/2004
Title:
FAST, ACCURATE AND LOW POWER SUPPLY VOLTAGE BOOSTER USING A/D CONVERTER
2
Patent #:
Issue Dt:
10/25/2005
Application #:
10634042
Filing Dt:
08/04/2003
Title:
A METHOD OF FABRICATING A DUAL-LEVEL STACKED FLASH MEMORY CELL WITH A MOSFET STORAGE TRANSISTOR
3
Patent #:
Issue Dt:
05/31/2005
Application #:
10654739
Filing Dt:
09/03/2003
Title:
PATTERNING FOR ELONGATED VSS CONTACT ON FLASH MEMORY
4
Patent #:
Issue Dt:
01/31/2006
Application #:
10655179
Filing Dt:
09/04/2003
Title:
MEMORY CELL STRUCTURE HAVING NITRIDE LAYER WITH REDUCED CHARGE LOSS AND METHOD FOR FABRICATING SAME
5
Patent #:
Issue Dt:
05/24/2005
Application #:
10678446
Filing Dt:
10/03/2003
Title:
EFFICIENT AND ACCURATE SENSING CIRCUIT AND TECHNIQUE FOR LOW VOLTAGE FLASH MEMORY DEVICES
6
Patent #:
Issue Dt:
11/08/2005
Application #:
10679179
Filing Dt:
10/03/2003
Title:
CIRCUIT AND TECHNIQUE FOR ACCURATELY SENSING LOW VOLTAGE FLASH MEMORY DEVICES
7
Patent #:
Issue Dt:
02/07/2006
Application #:
10700414
Filing Dt:
11/04/2003
Title:
MINIMIZATION OF FG-FG COUPLING IN FLASH MEMORY
8
Patent #:
Issue Dt:
01/11/2005
Application #:
10728510
Filing Dt:
12/05/2003
Title:
NEUTRON DETECTING DEVICE
9
Patent #:
Issue Dt:
11/08/2005
Application #:
10729732
Filing Dt:
12/05/2003
Title:
HARD MASK SPACER FOR SUBLITHOGRAPHIC BITLINE
10
Patent #:
Issue Dt:
03/29/2005
Application #:
10755430
Filing Dt:
01/12/2004
Title:
NARROW BITLINE USING SAFIER FOR MIRRORBIT
11
Patent #:
Issue Dt:
10/25/2005
Application #:
10755740
Filing Dt:
01/12/2004
Publication #:
Pub Dt:
07/14/2005
Title:
POCKET IMPLANT FOR COMPLEMENTARY BIT DISTURB IMPROVEMENT AND CHARGING IMPROVEMENT OF SONOS MEMORY CELL
12
Patent #:
Issue Dt:
11/30/2004
Application #:
10759809
Filing Dt:
01/16/2004
Title:
STRUCTURE FOR INCREASING DRIVE CURRENT IN A MEMORY ARRAY AND RELATED METHOD
13
Patent #:
Issue Dt:
04/11/2006
Application #:
10759855
Filing Dt:
01/16/2004
Title:
FLEXIBLE CASCODE AMPLIFIER CIRCUIT WITH HIGH GAIN FOR FLASH MEMORY CELLS
14
Patent #:
Issue Dt:
02/14/2006
Application #:
10795924
Filing Dt:
03/08/2004
Title:
SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE
15
Patent #:
Issue Dt:
04/18/2006
Application #:
10839561
Filing Dt:
05/04/2004
Title:
METHOD AND APPARATUS FOR ELIMINATING WORD LINE BENDING BY SOURCE SIDE IMPLANTATION
16
Patent #:
Issue Dt:
11/28/2006
Application #:
10839562
Filing Dt:
05/04/2004
Title:
POSITIVE GATE STRESS DURING ERASE TO IMPROVE RETENTION IN MULTI-LEVEL, NON-VOLATILE FLASH MEMORY
17
Patent #:
Issue Dt:
01/09/2007
Application #:
10839614
Filing Dt:
05/05/2004
Publication #:
Pub Dt:
11/10/2005
Title:
METHODS AND APPARATUS FOR WORDLINE PROTECTION IN FLASH MEMORY DEVICES
18
Patent #:
Issue Dt:
10/10/2006
Application #:
10841850
Filing Dt:
05/07/2004
Title:
FLASH MEMORY CELL AND METHODS FOR PROGRAMMING AND ERASING
19
Patent #:
Issue Dt:
01/24/2006
Application #:
10843289
Filing Dt:
05/11/2004
Publication #:
Pub Dt:
11/17/2005
Title:
BITLINE IMPLANT UTILIZING DUAL POLY
20
Patent #:
Issue Dt:
02/13/2007
Application #:
10862636
Filing Dt:
06/07/2004
Title:
LDC IMPLANT FOR MIRRORBIT TO IMPROVE VT ROLL-OFF AND FORM SHARPER JUNCTION
21
Patent #:
Issue Dt:
12/21/2004
Application #:
10863673
Filing Dt:
06/08/2004
Title:
MEMORY DEVICE AND METHODS OF USING NEGATIVE GATE STRESS TO CORRECT OVER-ERASED MEMORY CELLS
22
Patent #:
Issue Dt:
08/23/2005
Application #:
10863933
Filing Dt:
06/09/2004
Title:
RAMP SOURCE HOT-HOLE PROGRAMMING FOR TRAP BASED NON-VOLATILE MEMORY DEVICES
23
Patent #:
Issue Dt:
03/28/2006
Application #:
10968713
Filing Dt:
10/19/2004
Title:
PATTERNING FOR ELONGATED VSS CONTACT FLASH MEMORY
24
Patent #:
Issue Dt:
03/28/2006
Application #:
10981833
Filing Dt:
11/04/2004
Title:
RAMPED SOFT PROGRAMMING FOR CONTROL OF ERASE VOLTAGE DISTRIBUTIONS IN FLASH MEMORY DEVICES
25
Patent #:
Issue Dt:
10/17/2006
Application #:
11003208
Filing Dt:
12/02/2004
Title:
METHOD FOR ACHIEVING INCREASED CONTROL OVER INTERCONNECT LINE THICKNESS ACROSS A WAFER AND BETWEEN WAFERS
Assignor
1
Exec Dt:
01/31/2007
Assignee
1
915 DEGUIGNE DRIVE, P.O. BOX 3453
MAIL STOP 250
SUNNYVALE, CALIFORNIA 94088-3453
Correspondence name and address
RAYMOND E. FRITZ
915 DEGUIGNE DRIVE, P.O. BOX 3453
MAIL STOP 250
SUNNYVALE, CA 94088-3453

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