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Reel/Frame:	019185/0009			Pages:	11
		Recorded:	04/19/2007
Attorney Dkt #:	8195.020.NPUS01
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 1

1

Patent #:	7739629	Issue Dt:	06/15/2010	Application #:	11590657	Filing Dt:	10/30/2006
Publication #:	US20070245285	Pub Dt:	10/18/2007
Title:	METHOD AND MECHANISM FOR IMPLEMENTING ELECTRONIC DESIGNS HAVING POWER INFORMATION SPECIFICATIONS BACKGROUND

Assignors

1

Exec Dt:

03/28/2007

2

Exec Dt:

03/28/2007

3

Exec Dt:

03/28/2007

4

Exec Dt:

04/13/2007

5

Exec Dt:

04/13/2007

6

TSAI, HUAN-CHIH

Exec Dt:

04/10/2007

7

BHATIA, SANDEEP

Exec Dt:

04/01/2007

8

Exec Dt:

04/16/2007

9

Exec Dt:

03/30/2007

10

CHICKERMANE, VIVEK

Exec Dt:

03/30/2007

11

GALLAGHER, PATRICK

Exec Dt:

03/30/2007

Assignee

1

CADENCE DESIGN SYSTEMS, INC.

2655 SEELY AVENUE

BUILDING 5

SAN JOSE, CALIFORNIA 95134

Correspondence name and address
	STEPHEN C. DURANT
	1000 LOUISIANA
	SUITE 5350
	HOUSTON, CA 77002

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