|
Total properties:
73
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2001
|
Application #:
|
08872530
|
Filing Dt:
|
06/11/1997
|
|
Title:
|
SCHEDULING TECHNIQUES FOR DATA CELLS IN A DATA SWITCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2000
|
Application #:
|
08883147
|
Filing Dt:
|
06/27/1997
|
|
Title:
|
METHOD AND APPARATUS FOR DUAL ISSUE OF PROGRAM INSTRUCTIONS TO SYMMETRIC MULTIFUNCTIONAL EXECUTION UNITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2000
|
Application #:
|
08924604
|
Filing Dt:
|
09/05/1997
|
|
Title:
|
A WRITEBACK CACHE CELL WITH A DUAL PORTED DIRTY BIT CELL AND METHOD FOR OPERATING SUCH A CACHE CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2000
|
Application #:
|
08959056
|
Filing Dt:
|
10/28/1997
|
|
Title:
|
ASYNCHRONOUS TRANSFER MODE SWITCHING ARCHITECTURES HAVING CONNECTION BUFFERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2000
|
Application #:
|
08982822
|
Filing Dt:
|
12/02/1997
|
|
Title:
|
CACHE MEMORY CELL WITH A PRE-PROGRAMMED STATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2000
|
Application #:
|
09059614
|
Filing Dt:
|
04/13/1998
|
|
Title:
|
METHOD AND APPARATUS FOR COMMUNICATING SIGNALS BETWEEN CIRCUITS OPERATING AT DIFFERENT FREQUENCIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2000
|
Application #:
|
09059615
|
Filing Dt:
|
04/13/1998
|
|
Title:
|
SYSTEM BUS ARBITRATOR FOR FACILITATING MULTIPLE TRANSACTIONS IN A COMPUTER SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2001
|
Application #:
|
09060228
|
Filing Dt:
|
04/14/1998
|
|
Title:
|
ASYNCHRONOUS TRANSFER MODE TRAFFIC SHAPERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2002
|
Application #:
|
09062301
|
Filing Dt:
|
04/17/1998
|
|
Title:
|
METHOD AND APPARATUS FOR FORMING A VIRTUAL CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2001
|
Application #:
|
09126680
|
Filing Dt:
|
07/30/1998
|
|
Title:
|
CIRCUIT, ARCHITECTURE AND METHOD FOR ANALYZING THE OPERATION OF A DIGITAL PROCESSING SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2002
|
Application #:
|
09235148
|
Filing Dt:
|
01/21/1999
|
|
Title:
|
FLOATING-POINT AND INTEGER MULTIPLY-ADD AND MULTIPLY-ACCUMULATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
09277659
|
Filing Dt:
|
03/26/1999
|
|
Title:
|
APPARATUS AND METHOD FOR OPERATING A DUAL PORT MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2000
|
Application #:
|
09281620
|
Filing Dt:
|
03/30/1999
|
|
Title:
|
PROCESSOR WITH MULTIPLE EXECUTION UNITS AND LOCAL AND GLOBAL REGISTER BYPASSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2003
|
Application #:
|
09422045
|
Filing Dt:
|
10/20/1999
|
|
Title:
|
METHOD AND APPARATUS FOR VECTOR REGISTER WITH SCALAR VALUES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2003
|
Application #:
|
09519524
|
Filing Dt:
|
03/06/2000
|
|
Publication #:
|
|
Pub Dt:
|
12/26/2002
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR DUAL ISSUE OF PROGRAM INSTRUCTIONS TO SYMMETRIC MULTIFUNCTIONAL EXECUTION UNITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2001
|
Application #:
|
09562055
|
Filing Dt:
|
05/01/2000
|
|
Title:
|
Low-voltage CMOS phase-locked loop (PLL) for high-performance microprocessor clock generation
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2005
|
Application #:
|
09562056
|
Filing Dt:
|
05/01/2000
|
|
Title:
|
FLOATING POINT PIPELINE METHOD AND CIRCUIT FOR FAST INVERSE SQUARE ROOT CALCULATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2001
|
Application #:
|
09562057
|
Filing Dt:
|
05/01/2000
|
|
Title:
|
Digital programmable delay element
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
09562058
|
Filing Dt:
|
05/01/2000
|
|
Title:
|
Reduced line select decoder for a memory array
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2004
|
Application #:
|
09562061
|
Filing Dt:
|
05/01/2000
|
|
Title:
|
METHOD AND SYSTEM FOR REDUCING TAKEN BRANCH PENALTY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2004
|
Application #:
|
09562062
|
Filing Dt:
|
05/01/2000
|
|
Title:
|
SCALABLE REPLACEMENT METHOD AND SYSTEM IN A CACHE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2009
|
Application #:
|
09562071
|
Filing Dt:
|
05/01/2000
|
|
Title:
|
LOW-POWER CACHE SYSTEM AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2007
|
Application #:
|
09564715
|
Filing Dt:
|
05/03/2000
|
|
Title:
|
PIPELINED PROCESSING WITH COMMIT SPECULATION STAGING BUFFER AND LOAD/STORE CENTRIC EXCEPTION HANDLING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2002
|
Application #:
|
09569543
|
Filing Dt:
|
05/12/2000
|
|
Title:
|
CACHE MEMORY CELL WITH A PRE-PROGRAMMED STATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2002
|
Application #:
|
09569818
|
Filing Dt:
|
05/12/2000
|
|
Title:
|
SINGLE PHASE EDGE TRIGGER REGISTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2004
|
Application #:
|
09654717
|
Filing Dt:
|
09/05/2000
|
|
Title:
|
A HIGH PERFORMANCE METHOD AND SYSTEM FOR PROCESSING INFORMANTION ON AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2006
|
Application #:
|
09654718
|
Filing Dt:
|
09/05/2000
|
|
Title:
|
METHOD FOR COORDINATING INFORMATION FLOW BETWEEN COMPONENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2004
|
Application #:
|
09654759
|
Filing Dt:
|
09/05/2000
|
|
Title:
|
METHOD AND SYSTEM FOR INITIATING COMPUTATION UPOPN UNORDERED RECEIPT OF DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2006
|
Application #:
|
09753797
|
Filing Dt:
|
01/02/2001
|
|
Publication #:
|
|
Pub Dt:
|
05/24/2001
| | | | |
|
Title:
|
ASYNCHRONOUS TRANSFER MODE TRAFFIC SHAPERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2006
|
Application #:
|
09780054
|
Filing Dt:
|
02/09/2001
|
|
Publication #:
|
|
Pub Dt:
|
07/26/2001
| | | | |
|
Title:
|
SCHEDULING TECHNIQUES FOR DATA CELLS IN A DATA SWITCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2004
|
Application #:
|
09909316
|
Filing Dt:
|
07/19/2001
|
|
Title:
|
SYSTEM AND METHOD FOR A HIGH SPEED, BI-DIRECTIONAL, ZERO TURNAROUND TIME, PSEUDO DIFFERENTIAL BUS CAPABLE OF SUPPORTING ARBITRARY NUMBER OF DRIVERS AND RECEIVERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2008
|
Application #:
|
09939454
|
Filing Dt:
|
08/24/2001
|
|
Publication #:
|
|
Pub Dt:
|
05/30/2002
| | | | |
|
Title:
|
NETWORK SWITCH WITH A PARALLEL SHARED MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
09939464
|
Filing Dt:
|
08/24/2001
|
|
Publication #:
|
|
Pub Dt:
|
05/30/2002
| | | | |
|
Title:
|
PROGRAMMABLE INTEGRATED CIRCUIT FOR USE IN A NETWORK SWITCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2006
|
Application #:
|
09940148
|
Filing Dt:
|
08/24/2001
|
|
Publication #:
|
|
Pub Dt:
|
05/30/2002
| | | | |
|
Title:
|
NETWORK SWITCH FOR ROUTING NETWORK TRAFFIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2006
|
Application #:
|
09996865
|
Filing Dt:
|
11/27/2001
|
|
Title:
|
DYNAMIC CIRCUIT USING EXCLUSIVE STATES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2007
|
Application #:
|
10023623
|
Filing Dt:
|
12/17/2001
|
|
Publication #:
|
|
Pub Dt:
|
06/20/2002
| | | | |
|
Title:
|
ADAPTIVE LINK QUALITY MANAGEMENT FOR WIRELESS MEDIUM
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10023633
|
Filing Dt:
|
12/17/2001
|
|
Publication #:
|
|
Pub Dt:
|
06/20/2002
| | | | |
|
Title:
|
Network node with multi-medium interfaces
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2007
|
Application #:
|
10023963
|
Filing Dt:
|
12/17/2001
|
|
Publication #:
|
|
Pub Dt:
|
06/20/2002
| | | | |
|
Title:
|
HYBRID NETWORK TO CARRY SYNCHRONOUS AND ASYNCHRONOUS TRAFFIC OVER SYMMETRIC AND ASYMMETRIC LINKS
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10023972
|
Filing Dt:
|
12/17/2001
|
|
Publication #:
|
|
Pub Dt:
|
06/20/2002
| | | | |
|
Title:
|
Integration of network, data link, and physical layer to adapt network traffic
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2008
|
Application #:
|
10023974
|
Filing Dt:
|
12/17/2001
|
|
Publication #:
|
|
Pub Dt:
|
06/20/2002
| | | | |
|
Title:
|
DYNAMIC MIXING TDM DATA WITH DATA PACKETS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2007
|
Application #:
|
10093324
|
Filing Dt:
|
03/06/2002
|
|
Title:
|
INTERFACING 622.08 MHZ LINE INTERFACE TO A 77.76 MHZ SONET FRAMER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
10209079
|
Filing Dt:
|
07/31/2002
|
|
Title:
|
ADVANCED ERROR CORRECTING OPTICAL TRANSPORT NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2007
|
Application #:
|
10210750
|
Filing Dt:
|
07/31/2002
|
|
Title:
|
ADVANCED MULTI-PROTOCOL OPTICAL TRANSPORT NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2008
|
Application #:
|
10302015
|
Filing Dt:
|
11/21/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/27/2004
| | | | |
|
Title:
|
ADVANCED TELECOMMUNICATIONS ROUTER AND CROSSBAR SWITCH CONTROLLER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2009
|
Application #:
|
10452229
|
Filing Dt:
|
06/03/2003
|
|
Title:
|
ADVANCED COMMUNICATION APPARATUS AND METHOD FOR VERIFIED COMMUNICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2012
|
Application #:
|
10452563
|
Filing Dt:
|
05/30/2003
|
|
Title:
|
MULTI-PROTOCOL COMMUNICATION CIRCUIT
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10682579
|
Filing Dt:
|
10/08/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/27/2004
| | | | |
|
Title:
|
Advanced telecommunications processor
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
10687784
|
Filing Dt:
|
10/17/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
|
Title:
|
ENCODING-BASED MULTICAST PACKET DUPLICATION CONTROL SUITABLE FOR VLAN SYSTEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2007
|
Application #:
|
10687785
|
Filing Dt:
|
10/17/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR PROVIDING INTERNAL TABLE EXTENSIBILITY WITH EXTERNAL INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2009
|
Application #:
|
10687786
|
Filing Dt:
|
10/17/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR PACKET TRANSMIT QUEUE CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2008
|
Application #:
|
10687789
|
Filing Dt:
|
10/17/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR PROVIDING INTERNAL TABLE EXTENSIBILITY BASED ON PRODUCT CONFIGURATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/2009
|
Application #:
|
10703842
|
Filing Dt:
|
11/07/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR ENHANCED HASHING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2007
|
Application #:
|
10735107
|
Filing Dt:
|
12/12/2003
|
|
Title:
|
METHOD AND APPARATUS FOR IMPLEMENTING A SEARCH ENGINE USING AN SRAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2007
|
Application #:
|
10739874
|
Filing Dt:
|
12/17/2003
|
|
Title:
|
TECHNIQUE FOR DEALLOCATION OF MEMORY IN A MULTICASTING ENVIRONMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2008
|
Application #:
|
10789668
|
Filing Dt:
|
02/27/2004
|
|
Title:
|
METHOD AND APPARATUS FOR CONSTRUCTING A SEARCH KEY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2009
|
Application #:
|
10789791
|
Filing Dt:
|
02/27/2004
|
|
Title:
|
METHOD AND APPARATUS FOR ACTION GROUP GENERATION AND ARBITRATION IN A CLASSIFICATION ENGINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2009
|
Application #:
|
10826215
|
Filing Dt:
|
04/16/2004
|
|
Title:
|
STACKED NETWORK SWITCH USING RESILIENT PACKET RING COMMUNICATION PROTOCOL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2008
|
Application #:
|
10897576
|
Filing Dt:
|
07/23/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/10/2005
| | | | |
|
Title:
|
ADVANCED PROCESSOR SYSTEM USING REQUEST, DATA, SNOOP, AND RESPONSE RINGS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2008
|
Application #:
|
10898008
|
Filing Dt:
|
07/23/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/10/2005
| | | | |
|
Title:
|
ADVANCED PROCESSOR WITH SYSTEM ON A CHIP INTERCONNECT TECHNOLOGY
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10930175
|
Filing Dt:
|
08/31/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
|
Title:
|
Advanced processor with a thread aware return address stack optimally used across active threads
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/2009
|
Application #:
|
10930179
|
Filing Dt:
|
08/31/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
|
Title:
|
ADVANCED PROCESSOR WITH USE OF BRIDGES ON A DATA MOVEMENT RING FOR OPTIMAL REDIRECTION OF MEMORY AND I/O TRAFFIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2008
|
Application #:
|
10930186
|
Filing Dt:
|
08/31/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
|
Title:
|
ADVANCED PROCESSOR WITH SCHEME FOR OPTIMAL PACKET FLOW IN A MULTI-PROCESSOR SYSTEM ON A CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2008
|
Application #:
|
10930187
|
Filing Dt:
|
08/31/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/16/2006
| | | | |
|
Title:
|
ADVANCED PROCESSOR WITH IMPLEMENTATION OF MEMORY ORDERING ON A RING BASED DATA MOVEMENT NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2011
|
Application #:
|
10930456
|
Filing Dt:
|
08/31/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/24/2005
| | | | |
|
Title:
|
ADVANCED PROCESSOR WITH MECHANISM FOR ENFORCING ORDERING BETWEEN INFORMATION SENT ON TWO INDEPENDENT NETWORKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2015
|
Application #:
|
10930937
|
Filing Dt:
|
08/31/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/24/2005
| | | | |
|
Title:
|
ADVANCED PROCESSOR WITH INTERFACING MESSAGING NETWORK TO A CPU
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2012
|
Application #:
|
10930938
|
Filing Dt:
|
08/31/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/24/2005
| | | | |
|
Title:
|
MULTI-CORE MULTI-THREADED PROCESSING SYSTEMS WITH INSTRUCTION REORDERING IN AN IN-ORDER PIPELINE
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10930939
|
Filing Dt:
|
08/31/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/24/2005
| | | | |
|
Title:
|
Advanced processor with mechanism for maximizing resource usage in an in-order pipeline with multiple threads
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2011
|
Application #:
|
10931014
|
Filing Dt:
|
08/31/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
|
Title:
|
ADVANCED PROCESSOR WITH MECHANISM FOR PACKET DISTRIBUTION AT HIGH LINE RATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2011
|
Application #:
|
10968460
|
Filing Dt:
|
10/18/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
|
Title:
|
PREFIX MATCHING STRUCTURE AND METHOD FOR FAST PACKET SWITCHING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2011
|
Application #:
|
11093184
|
Filing Dt:
|
03/28/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/28/2006
| | | | |
|
Title:
|
MECHANISM FOR MANAGING ACCESS TO RESOURCES IN A HETEROGENEOUS DATA REDIRECTION DEVICE
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11236324
|
Filing Dt:
|
09/26/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/29/2007
| | | | |
|
Title:
|
Scaleable channel scheduler system and method
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2009
|
Application #:
|
11283154
|
Filing Dt:
|
11/18/2005
|
|
Publication #:
|
|
Pub Dt:
|
05/25/2006
| | | | |
|
Title:
|
HIGH PERFORMANCE INTEGRATED CIRCUIT WITH LOW SKEW CLOCKING NETWORKS AND IMPROVED LOW POWER OPERATING MODE HAVING REDUCED RECOVERY TIME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2010
|
Application #:
|
11652827
|
Filing Dt:
|
01/11/2007
|
|
Publication #:
|
|
Pub Dt:
|
07/17/2008
| | | | |
|
Title:
|
SYSTEMS AND METHODS FOR UTILIZING AN EXTENDED TRANSLATION LOOK-ASIDE BUFFER HAVING A HYBRID MEMORY STRUCTURE
|
|
