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Patent Assignment Details
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Reel/Frame:019367/0627   Pages: 2
Recorded: 05/10/2007
Attorney Dkt #:1095.1425
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
NONE
Issue Dt:
Application #:
11798165
Filing Dt:
05/10/2007
Publication #:
Pub Dt:
12/13/2007
Title:
METHOD OF DESIGNING AND MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING MASTER SLICE METHOD
Assignor
1
Exec Dt:
02/16/2007
Assignee
1
1-1, KAMIKODANAKA 4-CHOME NAKAHARA-KU, KAWASAKI-SHI
KANAGAWA 211-8588, JAPAN
Correspondence name and address
STAAS & HASLEY LLP
ATTN: WILLIAM F. HERBERT
1201 NEW YORK AVENUE, N.W., SUITE 700
WASHINGTON, D.C. 20005

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