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Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	019419/0954			Pages:	21
		Recorded:	06/11/2007
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 14

Patent #:	5577230	Issue Dt:	11/19/1996	Application #:	08288420	Filing Dt:	08/10/1994
Title:	APPARATUS AND METHOD FOR COMPUTER PROCESSING USING AN ENHANCED HARVARD ARCHITECTURE UTILIZING DUAL MEMORY BUSES AND THE ARBITRATION FOR DATA/INSTRUCTION FETCH

Patent #:	5941940	Issue Dt:	08/24/1999	Application #:	08884691	Filing Dt:	06/30/1997
Title:	DIGITAL SIGNAL PROCESSOR ARCHITECTURE FOR PERFORMING FAST FOURIER TRANSFORMS

Patent #:	5892729	Issue Dt:	04/06/1999	Application #:	08900773	Filing Dt:	07/25/1997
Title:	POWER SAVINGS FOR MEMORY ARRAYS

Patent #:	6446193	Issue Dt:	09/03/2002	Application #:	08925302	Filing Dt:	09/08/1997
Title:	METHOD AND APPARATUS FOR SINGLE CYCLE PROCESSING OF ACCUMULATOR PAIRS IN A DUAL MULTIPLY-ACCUMULATE ARCHITECTURE

Patent #:	6226726	Issue Dt:	05/01/2001	Application #:	09075946	Filing Dt:	05/12/1998
Title:	MEMORY BANK ORGANIZATION CORRELATING DISTANCE WITH A MEMORY MAP

Patent #:	6049498	Issue Dt:	04/11/2000	Application #:	09100124	Filing Dt:	06/19/1998
Title:	DOUBLE TRANSISTOR SWITCH FOR SUPPLYING MULTIPLE VOLTAGES TO FLASH MEMORY WORDLINES

Patent #:	6064712	Issue Dt:	05/16/2000	Application #:	09158927	Filing Dt:	09/23/1998
Title:	AUTORELOAD LOOP COUNTER

Patent #:	6256725	Issue Dt:	07/03/2001	Application #:	09205466	Filing Dt:	12/04/1998
Title:	SHARED DATAPATH PROCESSOR AND METHOD UTILIZING STACK-BASED AND REGISTER-BASED STORAGE SPACES

Patent #:	5986969	Issue Dt:	11/16/1999	Application #:	09217613	Filing Dt:	12/22/1998
Title:	POWER SAVINGS FOR MEMORY ARRAYS

Patent #:	5966317	Issue Dt:	10/12/1999	Application #:	09247633	Filing Dt:	02/10/1999
Title:	SHIELDED BITLINES FOR STATIC RAMS

Patent #:	6397240	Issue Dt:	05/28/2002	Application #:	09252500	Filing Dt:	02/18/1999
Title:	PROGRAMMABLE ACCELERATOR FOR A PROGRAMMABLE PROCESSOR SYSTEM

Patent #:	6184700	Issue Dt:	02/06/2001	Application #:	09318158	Filing Dt:	05/25/1999
Title:	FAIL SAFE BUFFER CAPABLE OF OPERATING WITH A MIXED VOLTAGE CORE

Patent #:	6282137	Issue Dt:	08/28/2001	Application #:	09395835	Filing Dt:	09/14/1999
Title:	SRAM METHOD AND APPARATUS

Patent #:	6178134	Issue Dt:	01/23/2001	Application #:	09401032	Filing Dt:	09/21/1999
Title:	STATIC RANDOM ACCESS MEMORY WITH GLOBAL BIT-LINES

Assignor

Exec Dt:

01/30/2001

Assignee

1110 AMERICAN PARKWAY NE

ALLENTOWN, PENNSYLVANIA 18109

Correspondence name and address
	DOCKET ADMINISTRATOR
	AGERE SYSTEMS INC.
	ROOM 4U-533C
	400 CONNELL DRIVE
	BERKELEY HEIGHTS, NEW JERSEY 07922-2747

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