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Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	019524/0042			Pages:	12
		Recorded:	06/29/2007
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 20

Patent #:	7130987	Issue Dt:	10/31/2006	Application #:	10351030	Filing Dt:	01/24/2003
Publication #:	US20040148415	Pub Dt:	07/29/2004
Title:	RECONFIGURABLE SEMANTIC PROCESSOR

Patent #:	7251722	Issue Dt:	07/31/2007	Application #:	10843727	Filing Dt:	05/11/2004
Publication #:	US20050268032	Pub Dt:	12/01/2005
Title:	SEMANTIC PROCESSOR STORAGE SERVER ARCHITECTURE

Patent #:	7398356	Issue Dt:	07/08/2008	Application #:	11181117	Filing Dt:	07/13/2005
Publication #:	US20060020756	Pub Dt:	01/26/2006
Title:	CONTEXTUAL MEMORY INTERFACE FOR NETWORK PROCESSOR

Patent #:	NONE	Issue Dt:		Application #:	11181149	Filing Dt:	07/13/2005
Publication #:	US20050281281	Pub Dt:	12/22/2005
Title:	Port input buffer architecture

Patent #:	7415596	Issue Dt:	08/19/2008	Application #:	11181527	Filing Dt:	07/14/2005
Publication #:	US20060010193	Pub Dt:	01/12/2006
Title:	PARSER TABLE/PRODUCTION RULE TABLE CONFIGURATION USING CAM AND SRAM

Patent #:	NONE	Issue Dt:		Application #:	11181528	Filing Dt:	07/14/2005
Publication #:	US20070027991	Pub Dt:	02/01/2007
Title:	TCP isolation with semantic processor TCP state machine

Patent #:	7451268	Issue Dt:	11/11/2008	Application #:	11181598	Filing Dt:	07/13/2005
Publication #:	US20060168324	Pub Dt:	07/27/2006
Title:	ARBITER FOR ARRAY MACHINE CONTEXT DATA MEMORY

Patent #:	NONE	Issue Dt:		Application #:	11181599	Filing Dt:	07/13/2005
Publication #:	US20060026377	Pub Dt:	02/02/2006
Title:	Lookup interface for array machine context data memory

Patent #:	7424571	Issue Dt:	09/09/2008	Application #:	11181611	Filing Dt:	07/13/2005
Publication #:	US20060026378	Pub Dt:	02/02/2006
Title:	ARRAY MACHINE CONTEXT DATA MEMORY

Patent #:	NONE	Issue Dt:		Application #:	11184424	Filing Dt:	07/18/2005
Publication #:	US20070016906	Pub Dt:	01/18/2007
Title:	Efficient hardware allocation of processes to processors

Patent #:	NONE	Issue Dt:		Application #:	11185223	Filing Dt:	07/19/2005
Publication #:	US20070043871	Pub Dt:	02/22/2007
Title:	Debug non-terminal symbol for parser error handling

Patent #:	NONE	Issue Dt:		Application #:	11186144	Filing Dt:	07/20/2005
Publication #:	US20070019661	Pub Dt:	01/25/2007
Title:	Packet output buffer for semantic processor

Patent #:	NONE	Issue Dt:		Application #:	11187049	Filing Dt:	07/21/2005
Publication #:	US20070022479	Pub Dt:	01/25/2007
Title:	Network interface and firewall device

Patent #:	NONE	Issue Dt:		Application #:	11187055	Filing Dt:	07/21/2005
Publication #:	US20070022225	Pub Dt:	01/25/2007
Title:	Memory DMA interface with checksum

Patent #:	NONE	Issue Dt:		Application #:	11189140	Filing Dt:	07/25/2005
Publication #:	US20070022275	Pub Dt:	01/25/2007
Title:	Processor cluster implementing conditional instruction skip

Patent #:	NONE	Issue Dt:		Application #:	11198748	Filing Dt:	08/04/2005
Publication #:	US20060031555	Pub Dt:	02/09/2006
Title:	Data context switching in a semantic processor

Patent #:	7478223	Issue Dt:	01/13/2009	Application #:	11365051	Filing Dt:	02/28/2006
Publication #:	US20060168309	Pub Dt:	07/27/2006
Title:	SYMBOL PARSING ARCHITECTURE

Patent #:	NONE	Issue Dt:		Application #:	11376512	Filing Dt:	03/14/2006
Publication #:	US20060174058	Pub Dt:	08/03/2006
Title:	Recirculation buffer for semantic processor

Assignor

Exec Dt:

06/28/2006

Assignee

2010 NORTH FIRST STREET

SAN JOSE, CALIFORNIA 95131

Correspondence name and address
	RUSSELL D. POLLOCK, ESQ.
	GREENE RADOVSKY MALONEY & SHARE LLP
	FOUR EMBARCADERO CENTER, SUITE 4000
	SAN FRANCISCO, CA 94111

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